ELANSC520-133AC Advanced Micro Devices, ELANSC520-133AC Datasheet

ELANSC520-133AC

Manufacturer Part Number

ELANSC520-133AC

Description

Manufacturer

Advanced Micro Devices

Datasheet

1.ELANSC520-133AC.pdf (105 pages)

Specifications of ELANSC520-133AC

Case

BGA

Date_code

08+

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Élan™SC520 Microcontroller

Integrated 32-Bit Microcontroller with PC/AT-Compatible Peripherals,

PCI Host Bridge, and Synchronous DRAM Controller

DISTINCTIVE CHARACTERISTICS

GENERAL DESCRIPTION

The Élan™SC520 microcontroller is a full-featured mi-

crocontroller developed for the general embedded

market. The ÉlanSC520 microcontroller combines a

32-bit, low-voltage Am5

grated peripherals suitable for both real-time and PC/

AT-compatible embedded applications.

An integrated PCI host bridge, SDRAM controller, enhanced

PC/AT-compatible peripherals, and advanced debugging

features provide the system designer with a wide range of

on-chip resources, allowing support for legacy devices as

well as new devices available in the current PC marketplace.

Industry-standard Am5

point unit (FPU) and 16-Kbyte write-back cache

– 100-MHz and 133-MHz operating frequencies

– Low-voltage operation (core V

– 5-V tolerant I/O (3.3-V output levels)

E86™ family of x86 embedded processors

– Part of a software-compatible family of

Integrated PCI host bridge controller leverages

standard peripherals and software

– 33 MHz, 32-bit PCI bus Revision 2.2-compliant

– High-throughput 132-Mbyte/s peak transfer

– Supports up to five external PCI masters

– Integrated write-posting and read-buffering for

Synchronous DRAM (SDRAM) controller

– Supports 16-, 64-, 128-, and 256-Mbit SDRAM

– Supports 4 banks for a total of 256 Mbytes

– Error Correction Code provides system reliability

– Buffers improve read and write performance

AMDebug™ technology offers a low-cost

solution for the advanced debugging

capabilities required by embedded designers

– Allows instruction tracing during execution from

– Uses an enhanced JTAG port for low-cost debugging

– Parallel debug port for high-speed data exchange

General-Purpose (GP) bus with programmable

timing for 8- and 16-bit devices provides good

performance at low cost

microprocessors and microcontrollers well

supported by a wide variety of development tools

high-throughput applications

the Am5

during in-circuit emulation

PRELIMINARY

86 CPU’s internal cache

86 CPU with a set of inte-

86® CPU with floating

= 2.5 V)

Designed for medium- to high-performance applications

in the telecommunications, data communications, and

information appliance markets, the ÉlanSC520 micro-

controller is particularly well suited for applications re-

quiring high throughput combined with low latency. The

compact Plastic Ball Grid Array (PBGA) package pro-

vides a high degree of functionality in a very small form

factor, making it cost-effective for many applications. A

0.25-micron CMOS manufacturing process allows for

low power consumption along with high performance.

ROM/Flash controller for 8-, 16-, and 32-bit devices

Enhanced PC/AT-compatible peripherals

provide improved performance

– Enhanced programmable interrupt controller

– Enhanced DMA controller includes double buffer

– Two 16550-compatible UARTs operate at baud

Standard PC/AT-compatible peripherals

– Programmable interval timer (PIT)

– Real-time clock (RTC) with battery backup

Additional integrated peripherals

– Three general-purpose 16-bit timers provide

– Watchdog timer guards against runaway software

– Software timer

– Synchronous serial interface (SSI) offers

– Flexible address decoding for programmable

32 programmable input/output (PIO) pins

Native support for pSOS, QNX, RTXC, VxWorks,

and Windows

Industry-standard BIOS support

Plastic Ball Grid Array (PBGA388) package

(PIC) prioritizes 22 interrupt levels (up to 15

external sources) with flexible routing

chaining, extended address and transfer counts,

and flexible channel routing

rates up to 1.15 Mbit/s with optional DMA interface

capability and 114 bytes of RAM

flexible cascading for 32-bit operation

full-duplex or half-duplex operation

memory and I/O mapping and system addressing

configuration

CE operating systems

Final Draft# 22003

Issue Date: March 2001

Rev: B Amendment/0

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