EPM7064SLC8410N Altera Corporation, EPM7064SLC8410N Datasheet

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EPM7064SLC8410N

Manufacturer Part Number
EPM7064SLC8410N
Description
PLCC84
Manufacturer
Altera Corporation
Datasheet

Specifications of EPM7064SLC8410N

Date_code
08+
Features...
Altera Corporation
DS-MAX7000-6.7
September 2005, ver. 6.7
Usable
gates
Macrocells
Logic array
blocks
Maximum
user I/O pins
t
t
t
t
f
PD
SU
FSU
CO1
CNT
Table 1. MAX 7000 Device Features
Feature
(ns)
(ns)
(ns)
(ns)
(MHz)
f
EPM7032
151.5
600
2.5
32
36
2
6
5
4
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devices, see the
Data Sheet
Sheet.
EPM7064
1,250
151.5
2.5
64
68
4
6
5
4
High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX
5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see
5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
PCI-compliant devices available
ISP circuitry compatible with IEEE Std. 1532
or the
EPM7096
®
1,800
125.0
7.5
4.5
96
76
6
6
3
MAX 7000B Programmable Logic Device Family Data
EPM7128E
2,500
125.0
Tables 1
MAX 7000A Programmable Logic Device Family
128
100
7.5
4.5
8
6
3
and 2)
EPM7160E
3,200
100.0
160
104
10
10
7
3
5
Programmable Logic
®
architecture
EPM7192E
3,750
90.9
192
124
Device Family
12
12
7
3
6
MAX 7000
Data Sheet
EPM7256E
5,000
90.9
256
164
16
12
7
3
6
1

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