FS613101 AMI Semiconductor, FS613101 Datasheet
FS613101
Manufacturer Part Number
FS613101
Description
SOP16
Manufacturer
AMI Semiconductor
Datasheet
1.FS613101.pdf
(39 pages)
Specifications of FS613101
Date_code
09+
ISO9001
ISO9001
ISO9001
ISO9001
1.0
2.0
The FS6131-01 is a monolithic CMOS clock genera-
tor/regenerator IC designed to minimize cost and compo-
nent count in a variety of electronic systems. Via the I
bus interface, the FS6131-01 can be adapted to many
clock generation requirements.
The ability to tune the on-board voltage-controlled crystal
oscillator (VCXO), the length of the Reference and Feed-
back Dividers, their granularity, and the flexibility of the
Post Divider make the FS6131-01 the most flexible
stand-alone phase-locked loop (PLL) clock generator
available.
Figure 2: Block Diagram
I
specifications as may be required to permit improvements in the design of its products.
2
C is a licensed trademark of Philips Electronics, N.V. Windows and Windows NT are registered trademarks of Microsoft Corporation. American Microsystems, Inc. reserves the right to change detail
Complete programmable control via I
Selectable CMOS or PECL compatible outputs
External feedback loop capability allows genlocking
Tunable VCXO loop for jitter attenuation
Commercial (FS6131-01) and industrial (FS6131-01i)
temperature versions available
(optional)
XOUT
REF
FBK
SCL
SDA
XTUNE
(optional)
XIN
ADDR
Features
Description
1
0
REFDSRC
Interface
(f
REF
VCXO
I
2
)
C
XCT[3:0],
XLVTEN
Reference
REFDIV[11:0]
Divider
(N
R
)
Registers
Control
Divider
VCXO
1
0
ROM
0
1
PDREF
PDFBK
Frequency
XLROM[2:0]
2
Detector
Phase-
C
ä
Frequency
-bus
Detector
Phase-
XLPDEN,
Divider
XLSWAP
Feedback
FBKDIV[13:0]
DOWN
UP
(N
CRYSTAL LOOP
Charge
MLCP[1:0]
Pump
F
)
2
C-
DOWN
UP
Charge
XLCP[1:0]
Pump
FBKDSRC[1:0]
3.0
Figure 1: Pin Configuration
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
11
Controlled
Oscillator
Voltage
OSCTYPE
VCOSPD,
01
10
00
Frequency Synthesis
Line-Locked and Genlock Applications
Clock Multiplication
Telecom Jitter Attenuation
Applications
00
01
10
(f
VCO
XTUNE
11
ADDR
XOUT
)
OUTMUX[1:0]
SDA
VDD
VSS
SCL
XIN
MAIN LOOP
Gobbler
EXTLF
Clock
GBL
Internal
16-pin 0.150" SOIC
Loop
Filter
1
2
3
4
5
6
7
8
0
LFTC
1
POST3[1:0]
POST2[1:0]
POST1[1:0]
Divider
(N
Post
Px
)
FS6131-01
FS6131-01
FS6131-01
FS6131-01
Detect
STAT[1:0]
FS6131
Lock
16
15
14
13
12
11
10
9
CMOS/PECL
CLKN
CLKP
VDD
FBK
REF
VSS
EXTLF
LOCK/IPRG
Output
1
0
CMOS
C
R
LF
LF
C
EXTLF
(optional)
LOCK/
IPRG
(optional)
CLKP
CLKN
LP
(f
CLK
)
2.27.02
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