ISPLSI1032E125LJ Lattice Semiconductor Corp., ISPLSI1032E125LJ Datasheet
![no-image](/images/manufacturer_photos/0/3/382/lattice_semiconductor_corp__sml.jpg)
ISPLSI1032E125LJ
Manufacturer Part Number
ISPLSI1032E125LJ
Description
PLCC84
Manufacturer
Lattice Semiconductor Corp.
Datasheets
1.ISPLSI1032E125LT.pdf
(17 pages)
2.ISPLSI1032E125LJ.pdf
(16 pages)
3.ISPLSI1032E125LJ.pdf
(16 pages)
Specifications of ISPLSI1032E125LJ
Date_code
04+
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISPLSI1032E125LJ
Manufacturer:
LAT
Quantity:
2 596
• HIGH DENSITY PROGRAMMABLE LOGIC
• HIGH PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
1032e_09
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Features
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
—
—
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
— Complete Programmable Device Can Combine Glue
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
— Lead-Free Package Options
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
Machines, Address Decoders, etc.
f
t
Market and Improved Product Quality
Logic and Structured Designs
Minimize Switching Noise
Interconnectivity
max = 125 MHz Maximum Operating Frequency
pd = 7.5 ns Propagation Delay
2
CMOS
®
TECHNOLOGY
1
In-System Programmable High Density PLD
The ispLSI 1032E is a High Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing
provides complete interconnectivity between all of these
elements. The ispLSI 1032E device offers 5V non-vola-
tile in-system programmability of the logic, as well as the
interconnects to provide truly reconfigurable systems. A
functional superset of the ispLSI 1032 architecture, the
ispLSI 1032E device adds two new global output enable
pins.
The basic unit of logic on the ispLSI 1032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 1032E device. Each GLB has 18 inputs, a pro-
grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
Functional Block Diagram
Description
A1
A2
A3
A4
A5
A6
A7
A0
D7 D6 D5 D4 D3 D2 D1 D0
B0 B1 B2 B3 B4 B5 B6 B7
Global Routing Pool (GRP)
Output Routing Pool
Output Routing Pool
ispLSI
Logic
Array
D Q
D Q
D Q
D Q
Pool (GRP). The GRP
GLB
®
1032E
CLK
C7
C6
C5
C4
C3
C2
C1
C0
August 2006
0139A(A1)-isp