MACH21512JC Advanced Micro Devices, MACH21512JC Datasheet

MACH21512JC

Manufacturer Part Number

MACH21512JC

Description

PLCC44

Manufacturer

Advanced Micro Devices

Datasheet

1.MACH21512JC.pdf (30 pages)

Specifications of MACH21512JC

Date_code

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MACH215-12/15/20

High-Density EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

GENERAL DESCRIPTION

The MACH215 is a member of the high-performance

EE CMOS MACH device family. This device has

approximately three times the capability of the popular

PAL20RA10 without loss of speed. This device is

designed for use in asynchronous as well as synchro-

nous applications.

The MACH215 consists of four PAL blocks intercon-

nected by a programmable switch matrix. The four PAL

blocks are essentially “PAL22RA8” structures complete

with product-term arrays and programmable macro-

cells, individual register control product terms, and input

registers. The switch matrix connects the PAL blocks to

each other and to all input pins, providing a high degree

of connectivity between the fully-connected PAL blocks.

This allows designs to be placed and routed efficiently.

44 Pins

32 Output Macrocells

32 Input Macrocells

Product terms for:

— Individual flip-flop clock

— Individual asynchronous reset, preset

— Individual output enable

12 ns t

14.5 ns t

67 MHz f

FINAL

CNT

Commercial

Industrial

COM’L: -12/15/20

The MACH215 has two kinds of macrocell: output and

input. The MACH215 output macrocell provides regis-

tered, latched, or combinatorial outputs with program-

mable polarity. If a registered configuration is chosen,

the register can be configured as D-type or T-type to

help reduce the number of product terms. The register

type decision can be made by the designer or by the

software. Each macrocell has its own dedicated clock,

asynchronous reset, and asynchronous preset control.

The polarity of the clock signal is programmable. All

output macrocells can be connected to an I/O cell.

The MACH215 has dedicated input macrocells which

provide input registers or latches for synchronizing input

signals and reducing setup time requirements.

IND: -14/18/24

38 Inputs with pull-up resistors

32 Outputs

64 Flip-flops

For asynchronous and synchronous

applications

4 “PAL22RA8” blocks with buried macrocells

Pin-compatible with MACH110, MACH111,

MACH210, and MACH211

Lattice Semiconductor

Publication# 16751 Rev. E

Issue Date: May 1995

Amendment/0

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