EP910PC-35 Altera Corporation, EP910PC-35 Datasheet

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EP910PC-35

Manufacturer Part Number
EP910PC-35
Description
Manufacturer
Altera Corporation
Datasheet

Specifications of EP910PC-35

Package
DIP
Date_code
09+
Features
Altera Corporation
A-DS-CLASSIC-05
May 1999, ver. 5
Usable gates
Macrocells
Maximum user I/O pins
t
f
Table 1. Classic Device Features
PD
CNT
Complete device family with logic densities of 300 to 900 usable gates
(see
Device erasure and reprogramming with non-volatile EPROM
configuration elements
Fast pin-to-pin logic delays as low as 10 ns and counter frequencies
as high as 100 MHz
24 to 68 pins available in dual in-line package (DIP), plastic J-lead
chip carrier (PLCC), pin-grid array (PGA), and small-outline
integrated circuit (SOIC) packages
Programmable security bit for protection of proprietary designs
100% generically tested to provide 100% programming yield
Programmable registers providing D, T, JK, and SR flipflops with
individual clear and clock controls
Software design support featuring the Altera
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000
workstations, and third-party development systems
Programming support with Altera’s Master Programming Unit
(MPU); programming hardware from Data I/O, BP Microsystems,
and other third-party programming vendors
Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and
other interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and VeriBest
(ns)
(MHz)
Table
Feature
®
1)
EP610
EP610I
300
100
16
22
10
EP910
EP910I
76.9
450
24
38
12
®
MAX+PLUS
EPLD Family
Classic
Data Sheet
EP1810
®
900
48
64
20
50
II
745

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