MC100LVEL05DTG ON Semiconductor, MC100LVEL05DTG Datasheet

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MC100LVEL05DTG

Manufacturer Part Number
MC100LVEL05DTG
Description
IC GATE AND/NAND ECL 2INP 8TSSOP
Manufacturer
ON Semiconductor
Series
100LVELr
Datasheet

Specifications of MC100LVEL05DTG

Logic Type
AND/NAND Gate
Number Of Circuits
1
Number Of Inputs
2 Input (1, 1)
Schmitt Trigger Input
No
Output Type
Differential
Voltage - Supply
3 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-TSSOP
Product
MUX Gates
Logic Family
ECL
High Level Output Current
- 50 mA
Low Level Output Current
50 mA
Propagation Delay Time
0.44 ns
Supply Voltage (max)
+/- 3.8 V
Supply Voltage (min)
+/- 3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
MC100LVEL05DTGOS

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC100LVEL05DTG
Manufacturer:
ON
Quantity:
4 900
MC100LVEL05
3.3V ECL 2‐Input Differential
AND/NAND
Description
device is functionally equivalent to the MC100EL05 device and
operates from a 3.3 V supply voltage. With propagation delays and
output transition times equivalent to the EL05, the LVEL05 is ideally
suited for those applications which require the ultimate in AC
performance at low voltage power supplies.
function, the differential inputs and outputs of the device allows the
LVEL05 to also be used as a 2-input differential OR/NOR gate.
Features
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 4
The MC100LVEL05 is a 2-input differential AND/NAND gate. The
Because a negative 2-input NAND is equivalent to a 2-input OR
>200 V Machine Model
with V
with V
For Additional Information, see Application Note AND8003/D
Oxygen Index: 28 to 34
340 ps Propagation Delay
High Bandwidth Output Transitions
ESD Protection: >4 kV Human Body Model,
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
NECL Mode Operating Range: V
Internal Input Pulldown Resistors
Q Output will Default LOW with All Inputs Open or at V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
Flammability Rating: UL 94 V−0 @ 0.125 in,
Transistor Count = 69 devices
Pb−Free Packages are Available
EE
EE
= 0 V
= −3.0 V to −3.8 V
CC
CC
= 3.0 V to 3.8 V
= 0 V
EE
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
CASE 506AA
CASE 948R
MN SUFFIX
*For additional marking information, refer to
DT SUFFIX
CASE 751
D SUFFIX
TSSOP−8
8
(Note: Microdot may be in either location)
Application Note AND8002/D.
SOIC−8
8
DFN8
ORDERING INFORMATION
1
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
http://onsemi.com
Publication Order Number:
DIAGRAMS*
8
1
MARKING
MC100LVEL05/D
8
1
ALYWG
1
KVL05
ALYW
KV05
G
G
4

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MC100LVEL05DTG Summary of contents

Page 1

MC100LVEL05 3.3V ECL 2‐Input Differential AND/NAND Description The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3 V supply voltage. With propagation delays and output transition times equivalent to ...

Page 2

Figure 1. Logic Diagram and Pinout Assignment Table 2. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode ...

Page 3

Table 3. LVPECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Input ...

Page 4

Table 5. AC CHARACTERISTICS V CC Symbol Characteristic f Maximum Toggle Frequency max t Propagation Delay to Output PLH t PHL t Cycle−to−Cycle Jitter JITTER V Input Swing (Note Output Rise/Fall Times (20% − ...

Page 5

... ORDERING INFORMATION Device MC100LVEL05D MC100LVEL05DG MC100LVEL05DR2 MC100LVEL05DR2G MC100LVEL05DT MC100LVEL05DTG MC100LVEL05DTR2 MC100LVEL05DTR2G MC100LVEL05MNR4 MC100LVEL05MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D ...

Page 6

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 7

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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