IDT74FCT388915T133 Integrated Device Technology, Inc., IDT74FCT388915T133 Datasheet

IDT74FCT388915T133

Manufacturer Part Number

IDT74FCT388915T133

Description

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.IDT74FCT388915T133J.pdf (11 pages)

Specifications of IDT74FCT388915T133

Case

PLCC/28

Date_code

00+

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3.3V LOW SKEW PLL-BASED CLOCK DRIVER

FEATURES:

• 0.5 MICRON CMOS Technology

• Input frequency range: 10MHz – f2Q Max. spec

• Max. output frequency: 150MHz

• Pin and function compatible with FCT88915T, MC88915T

• 5 non-inverting outputs, one inverting output, one 2x

• 3-State outputs

• Output skew < 350ps (max.)

• Duty cycle distortion < 500ps (max.)

• Part-to-part skew: 1ns (from t

• 32/–16mA drive at CMOS output voltage levels

• V

• Inputs can be driven by 3.3V or 5V components

• Available in 28 pin PLCC, LCC and SSOP packages

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL BLOCK DIAGRAM

FEEDBACK

DESCRIPTION:

ogy to lock the frequency and phase of outputs to the input

reference clock. It provides low skew clock distribution for

high performance PCs and workstations. One of the outputs

FREQ_SEL

1995 Integrated Device Technology, Inc.

(FREQ_SEL = HIGH)

output, one 2 output; all outputs are TTL-compatible

REF_SEL

Integrated Device Technology, Inc.

SYNC (0)

SYNC (1)

The IDT54/74FCT388915T uses phase-lock loop technol-

PLL_EN

OE/RST

= 3.3V

0.3V

Phase/Freq.

Detector

Divide

-By-2

max. spec)

Mux

3.3V LOW SKEW PLL-BASED

CMOS CLOCK DRIVER

(WITH 3-STATE)

( 1)

( 2)

Charge Pump

9.8

is fed back to the PLL at the FEEDBACK input resulting in

essentially zero delay across the device. The PLL consists of

the phase/frequency detector, charge pump, loop filter and

VCO. The VCO is designed for a 2Q operating frequency

range of 40MHz to f2Q Max.

skew. The

runs at twice the Q frequency and Q/2 runs at half the Q

frequency.

the output path. PLL _EN allows bypassing of the PLL, which

is useful in static test modes. When PLL_EN is low, SYNC

input may be used as a test clock. In this test mode, the input

frequency is not limited to the specified range and the polarity

of outputs is complementary to that in normal operation

(PLL_EN = 1). The LOCK output attains logic HIGH when the

PLL is in steady-state phase and frequency lock. When OE/

RST

registers at Q,

component as recommended in Figure 3.

The IDT54/74FCT388915T provides 8 outputs with 350ps

The FREQ_SEL control provides an additional 2 option in

The IDT54/74FCT388915T requires one external loop filter

is low, all the outputs are put in high impedance state and

MILITARY AND COMMERCIAL TEMPERATURE RANGES

output is inverted from the Q outputs. The 2Q

and Q/2 outputs are reset.

Controlled

Oscilator

Voltage

IDT54/74FCT388915T

70/100/133/150

PRELIMINARY

LOCK

Q/2

AUGUST 1995

3052 drw 01

DSC-4243/1

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