DM74AS280N Fairchild Semiconductor, DM74AS280N Datasheet

IC PARITY GEN/CHKER 9BIT 14DIP

DM74AS280N

Manufacturer Part Number
DM74AS280N
Description
IC PARITY GEN/CHKER 9BIT 14DIP
Manufacturer
Fairchild Semiconductor
Series
74ASr
Datasheet

Specifications of DM74AS280N

Logic Type
Parity Generator/Checker
Number Of Circuits
9-Bit
Current - Output High, Low
2mA, 20mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
14-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74AS280
© 2000 Fairchild Semiconductor Corporation
DM74AS280M
DM74AS280N
DM74AS280
9-Bit Parity Generator/Checker
General Description
These universal, 9-bit parity generators/checkers utilize
advanced Schottky high performance circuitry and feature
odd/even outputs to facilitate operation of either odd or
even parity applications. The word length capability is eas-
ily expanded by cascading.
The DM74AS280 can be used to upgrade the performance
of most systems utilizing the ’180 parity generator/checker.
Although
expander inputs, the corresponding function is provided by
the availability of an input at pin 4 and no internal connec-
tion at pin 3. This permits the DM74AS280 to be substi-
tuted for the ’180 in existing designs to produce identical
function even if DM74AS280s are mixed with existing
’180s.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
the
DM74AS280
Package Number
M14A
N14A
is
implemented
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006303
without
Features
Function Table
L
H
Number of Inputs (A thru I)
Generates either odd or even parity for nine data lines
Inputs are buffered to lower the drive requirements
Can be used to upgrade existing systems using MSI
parity circuits
Cascadable for N-bits
Advanced oxide-isolated, ion-implanted Schottky
TTL process
Switching specifications at 50 pF
Switching specifications guaranteed over full
temperature and V
LOW State
HIGH State
Package Description
that are HIGH
0, 2, 4, 6, 8
1, 3, 5, 7, 9
CC
range
October 1986
Revised March 2000
Even
H
L
www.fairchildsemi.com
Outputs
Odd
H
L

Related parts for DM74AS280N

DM74AS280N Summary of contents

Page 1

... Package Number DM74AS280M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74AS280N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input ...

Page 4

Typical Applications Three DM74AS280s can be used to implement a 25-line parity generator/checker alternative, the outputs of two or three parity genera- tors/checkers can be decoded with a 2-input (AS86 FIGURE 2. 81-Line Parity/Generator Checker www.fairchildsemi.com ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M14A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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