74ABT899CMSA Fairchild Semiconductor, 74ABT899CMSA Datasheet

TXRX W/GENERATOR&CHECKER 28SSOP

74ABT899CMSA

Manufacturer Part Number
74ABT899CMSA
Description
TXRX W/GENERATOR&CHECKER 28SSOP
Manufacturer
Fairchild Semiconductor
Series
74ABTr
Datasheet

Specifications of 74ABT899CMSA

Logic Type
Parity Generator/Checker
Number Of Circuits
9-Bit
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 1999 Fairchild Semiconductor Corporation
74ABT899CSC
74ABT899CMSA
74ABT899CQC
74ABT899
9-Bit Latchable Transceiver
with Parity Generator/Checker
General Description
The ABT899 is a 9-bit to 9-bit parity transceiver with trans-
parent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction.
The ABT899 features independent latch enables for the A-
to-B direction and the B-to-A direction, a select pin for
ODD/EVEN parity, and separate error signal output pins for
checking parity.
Features
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
Order Number
Latchable transceiver with output sink of 64 mA
Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
Independent latch enables for A-to-B and B-to-A
directions
Select pin for ODD/EVEN parity
ERRA and ERRB output pins for parity checking
Package Number
Pin Assignment
MSA28
for PLCC
M28B
V28A
28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body
28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square
DS011509.prf
Ability to simultaneously generate and check parity
May be used in systems applications in place of the
543 and 280
May be used in system applications in place of the
657 and 373 (no need to change T/R to check parity)
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and
250 pF loads
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Nondestructive hot insertion capability
Disable time less than enable time to avoid bus
contention
Package Description
Pin Assignment for
SOIC and SSOP
November 1992
Revised January 1999
www.fairchildsemi.com

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74ABT899CMSA Summary of contents

Page 1

... Order Number Package Number 74ABT899CSC M28B 28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body 74ABT899CMSA MSA28 28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT899CQC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square Devices also available in Tape and Reel. Specify by appending suffix letter “ ...

Page 2

Pin Descriptions Pin Names Descriptions A –A A Bus Data Inputs/Data Outputs –B B Bus Data Inputs/Data Outputs 0 7 APAR, BPAR A and B Bus Parity Inputs/Outputs ODD/EVEN ODD/EVEN Parity Select, Active LOW for EVEN Parity ...

Page 3

Functional Block Diagram 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic V Pin Potential to CC Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disable or Power- Off ...

Page 5

DC Electrical Characteristics (PLCC package) Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V ...

Page 6

AC Electrical Characteristics (SSOP Package) Symbol Parameter t Propagation Delay PLH PHL Propagation Delay PLH BPAR, APAR PHL Propagation Delay PLH ...

Page 7

Extended AC Electrical Characteristics (SOIC and PLCC Package) Symbol Parameter f Max Toggle Frequency TOGGLE t Propagation Delay PLH PHL Propagation Delay PLH t APAR to BPAR PHL t Propagation Delay PLH t ...

Page 8

Extended AC Electrical Characteristics (SSOP Package) Symbol Parameter f Max Toggle Frequency TOGGLE t Propagation Delay PLH PHL Propagation Delay PLH t APAR to BPAR PHL t Propagation Delay PLH ...

Page 9

Skew (Note 2) (PLCC package) Symbol Parameter t Pin to Pin Skew OSHL (Note 21) HL Transitions t Pin to Pin Skew OSLH (Note 21) LH Transitions t Duty Cycle PS (Note 22) LH–HL Skew t Pin to Pin Skew ...

Page 10

AC Path A , APAR B , BPAR BPAR A , APAR BPAR n (B APAR ERRA n (B ERRB) n O/E ERRA O/E ERRB www.fairchildsemi.com FIGURE 1. FIGURE 2. FIGURE ...

Page 11

AC Path (Continued) O/E BPAR (O/E APAR) APAR ERRA (BPAR ERRB) ZH, HZ FIGURE 5. FIGURE 6. FIGURE 7. FIGURE 8. 11 www.fairchildsemi.com ...

Page 12

AC Path (Continued) ZL, LZ SEL BPAR (SEL APAR) LEA BPAR, B[0:7] (LEB APAR, A[0:7]) TS(H), TH(H) LEA APAR, A[0:7] (LEB BPAR, B[0:7]) www.fairchildsemi.com FIGURE 9. FIGURE 10. FIGURE 11. FIGURE 12. 12 ...

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AC Path (Continued) TS(L), TH(L) LEA APAR, A[0:7] (LEB BPAR, B[0:7]) FIGURE 13. FIGURE 14. 13 www.fairchildsemi.com ...

Page 14

AC Loading *Includes jig and probe capacitance FIGURE 15. Standard AC Test Load Amplitude 3.0V FIGURE 17. Test Input Signal Requirements AC Waveforms FIGURE 18. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 19. Propagation Delay, Pulse Width Waveforms ...

Page 15

Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body 28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number M28B Package Number MSA28 15 www.fairchildsemi.com ...

Page 16

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS ...

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