MM74HC165N Fairchild Semiconductor, MM74HC165N Datasheet

MM74HC165N

Manufacturer Part Number

MM74HC165N

Description

IC REGIST PAR-IN/SER-OUT 16-DIP

Manufacturer

Fairchild Semiconductor

Series

74HCr

Datasheet

1.MM74HC165N.pdf (8 pages)

Specifications of MM74HC165N

Logic Type

Shift Register

Output Type

Differential

Number Of Elements

Number Of Bits Per Element

Function

Parallel or Serial to Serial

Voltage - Supply

2 V ~ 6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Through Hole

Package / Case

16-DIP (0.300", 7.62mm)

Counting Sequence

Serial/Parallel to Serial

Number Of Circuits

Logic Family

74HC

Propagation Delay Time

150 ns, 30 ns, 26 ns

Supply Voltage (max)

6 V

Maximum Operating Temperature

+ 85 C

Minimum Operating Temperature

- 40 C

Mounting Style

Through Hole

Operating Supply Voltage

2 V to 6 V

Shift Register Function

Parallel To Serial

No. Of Elements

Ic Output Type

Differential

Logic Case Style

DIP

No. Of Pins

Supply Voltage Range

2V To 6V

Rohs Compliant

Yes

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

74HC165

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

MM74HC165N

Manufacturer:

NS/国半

Quantity:

20 000

Current page: 1 of 8
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MM74HC165M

MM74HC165SJ

MM74HC165MTC

MM74HC165

Parallel-in/Serial-out 8-Bit Shift Register

General Description

The MM74HC165 high speed PARALLEL-IN/SERIAL-OUT

SHIFT REGISTER utilizes advanced silicon-gate CMOS

technology. It has the low power consumption and high

noise immunity of standard CMOS integrated circuits,

along with the ability to drive 10 LS-TTL loads.

This 8-bit serial shift register shifts data from Q

when clocked. Parallel inputs to each stage are enabled by

a low level at the SHIFT/LOAD input. Also included is a

gated CLOCK input and a complementary output from the

eighth bit.

Clocking is accomplished through a 2-input NOR gate per-

mitting one input to be used as a CLOCK INHIBIT function.

Holding either of the CLOCK inputs high inhibits clocking,

and holding either CLOCK input low with the SHIFT/LOAD

input high enables the other CLOCK input. Data transfer

occurs on the positive going edge of the clock. Parallel

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Order Number

Pin Assignments for DIP, SOIC, SOP and TSSOP

Package Number

Top View

MTC16

M16D

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

DS005316.prf

to Q

loading is inhibited as long as the SHIFT/LOAD input is

HIGH. When taken LOW, data at the parallel inputs is

loaded directly into the register independent of the state of

the clock.

The 74HC logic family is functionally as well as pin-out

compatible with the standard 74LS logic family. All inputs

are protected from damage due to static discharge by inter-

nal diode clamps to V

Features

Function Table

cated steady-state input conditions were established.

clock; indicates a one-bit shift.

Shift/ Clock Clock Serial Parallel Outputs

Load Inhibit

Typical propagation delay: 20 ns (clock to Q)

Wide operating supply voltage range: 2–6V

Low input current: 1 A maximum

Low quiescent supply current: 80 A maximum (74HC

Series)

Fanout of 10 LS-TTL loads

Transition from LOW-to-HIGH level

Irrelevant (any input, including transitions)

, Q

HIGH Level (steady state), L

, Q

Package Description

The level of Q

Inputs

or Q

and ground.

, Q

before the most recent

LOW Level (steady state)

, or Q

September 1983

Revised February 1999

A. . .H Q

a. . .h

, respectively, before the indi-

www.fairchildsemi.com

Internal Output

transition of the

Related parts for MM74HC165N

MM74HC165N Summary of contents

Page 1

... Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View © 1999 Fairchild Semiconductor Corporation loading is inhibited as long as the SHIFT/LOAD input is HIGH. When taken LOW, data at the parallel inputs is loaded directly into the register independent of the state of the clock ...

Page 2

Logic Diagrams www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Clamp Diode Current ( Output Current, per pin (I ) OUT DC ...

Page 4

AC Electrical Characteristics Symbol Parameter f Maximum Operating Frequency MAX Maximum Propagation Delay PHL PLH t , ...

Page 5

AC Electrical Characteristics Symbol Parameter C Power Dissipation (per package) PD Capacitance (Note 5) C Maximum Input Capacitance IN Note 5: C determines the no load dynamic power consumption ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M16A Package Number M16D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), MS-001, 0.300” Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL ...

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