GS8162Z36BB-250I GSI Technology, GS8162Z36BB-250I Datasheet

GS8162Z36BB-250I

Manufacturer Part Number

GS8162Z36BB-250I

Description

Manufacturer

GSI Technology

Datasheet

1.GS8162Z18BB-150.pdf (34 pages)

Specifications of GS8162Z36BB-250I

Pack_quantity

Comm_code

85423245

Lead_time

Current page: 1 of 34
Download datasheet (2Mb)

119- & 165-Bump BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• On-chip parity encoding and error detection

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-bump and 165-bump BGA packages

• RoHS-compliant 119-bump and 165-bump BGA packages

Functional Description

The GS8162Z18/36B(B/D) is an 18Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Rev: 1.05 7/2007

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

available

Flow Through

Pipeline

3-1-1-1

2-1-1-1

18Mb Pipelined and Flow Through

Synchronous NBT SRAM

Curr

tCycle

Parameter Synopsis

(x18)

(x36)

(x18)

(x36)

1/34

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8162Z18/36B(B/D) may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8162Z18/36B(B/D) is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 119-bump or 165-bump BGA package.

-250

295

345

225

255

2.5

4.0

5.5

-200

245

285

200

220

3.0

5.0

6.5

-150

200

225

185

205

3.8

6.7

7.5

Unit

GS8162Z18/36B(B/D)

250 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

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