MT48LC8M16A2P-6A:GTR Micron Semiconductor Products, MT48LC8M16A2P-6A:GTR Datasheet

MT48LC8M16A2P-6A:GTR

Manufacturer Part Number

MT48LC8M16A2P-6A:GTR

Description

Manufacturer

Micron Semiconductor Products

Datasheet

1.MT48LC16M8A2P75G.pdf (74 pages)

Specifications of MT48LC8M16A2P-6A:GTR

Pack_quantity

1000

Comm_code

85423231

Lead_time

Eccn

EAR99

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SDRAM

MT48LC32M4A2 – 8 Meg x 4 x 4 banks

MT48LC16M8A2 – 4 Meg x 8 x 4 banks

MT48LC8M16A2 – 2 Meg x 16 x 4 banks

For the latest data sheet, refer to Micron’s Web site:

Features

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive edge

• Internal pipelined operation; column address can be

• Internal banks for hiding row access/precharge

• Programmable burst lengths (BL): 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge, and

• Self refresh mode; standard and low power

• 64ms, 4,096-cycle refresh (15.625µs/row)

• LVTTL-compatible inputs and outputs

• Single +3.3 ±0.3V power supply

Notes:

PDF: 09005aef8091e66d/Source: 09005aef8091e625

128MSDRAM_1.fm - Rev. M 10/07 EN

Options

• Configurations

• Write recovery (

• Package/Pinout

• Timing (cycle time)

• Self refresh

• Design revision

• Operating temperature range

of system clock

changed every clock cycle

auto refresh modes

– 32 Meg x 4 (8 Meg x 4 x 4 banks)

– 16 Meg x 8 (4 Meg x 8 x 4 banks)

– 8 Meg x 16 (2 Meg x 16 x 4 banks)

–

– Plastic package – OCPL

– 54-pin TSOP II (400 mil)

– 54-pin TSOP II (400 mil) Pb-free

– 60-ball FBGA (8mm x 16mm)

– 60-ball FBGA (8mm x 16mm) Pb-free

– 54-ball VFBGA (8mm x 8mm)

– 54-ball VFBGA (8mm x 8mm) Pb-free

– 7.5ns @ CL = 3 (PC133)

– 7.5ns @ CL = 2 (PC133)

– 6.0ns @ CL = 3 (x16 only)

– Standard

– Low power

– Commercial (0°C to +70°C)

– Industrial (–40°C to +85°C)

WR = “2 CLK”

1. Refer to Micron technical note: TN-48-05.

2. Off-center parting line.

3. Consult Micron for availability.

4. x16 only.

Products and specifications discussed herein are subject to change by Micron without notice.

WR)

Designator

32M4

16M8

8M16

None

-6A

-75

-7E

www.micron.com

Figure 1:

Notes:

Table 1:

Table 2:

Configuration

Refresh count

Row addressing

Bank addressing

Column addressing

Speed

Grade

-6A

-7E

-75

DQ0

DQ1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1. The # symbol indicates signal is active LOW. A dash (-) indicates

DQ0

DQ1

DQ2

DQ3

x8 and x4 pin function is same as x16 pin function.

Frequency

DQML

x16

CAS#

RAS#

167 MHz

143 MHz

133 MHz

100 MHz

VssQ

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

WE#

BA0

BA1

A10

CS#

Clock

Address Table

Key Timing Parameters

CL = CAS (Read) latency

54-Pin TSOP Pin Assignment

(Top View)

8 Meg x 4 x 4

4 (BA0, BA1)

32 Meg x 4

4K (A0–A11)

2K (A0–A9,

128Mb: x4, x8, x16 SDRAM

banks

A11)

CL = 2

5.4ns

6ns

Access Time

–

CL = 3

4 Meg x 8 x 4

4K (A0–A11)

4 (BA0, BA1)

5.4ns

16 Meg x 8

1K (A0–A9)

–

banks

Setup

Time

x16

Vss

DQ15

VssQ

DQ14

DQ13

DQ12

DQ11

VssQ

DQ10

DQ9

DQ8

Vss

DQMH

CLK

CKE

A11

Vss

1.5ns

2 Meg x 16 x 4

Features

4K (A0–A11)

4 (BA0, BA1)

8 Meg x 16

512 (A0–A8)

DQ7

DQ6

DQ5

DQ4

DQM

banks

DQ3

DQ2

DQM

Hold

Time

0.8ns

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