74VCX162839MTDX Fairchild Semiconductor, 74VCX162839MTDX Datasheet
74VCX162839MTDX
Specifications of 74VCX162839MTDX
Related parts for 74VCX162839MTDX
74VCX162839MTDX Summary of contents
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... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2000 Fairchild Semiconductor Corporation Features Compatible with PC100 and PC133 DIMM module specifications 1.65V– ...
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Connection Diagram Logic Diagram www.fairchildsemi.com Truth Table Inputs I CLK REGE Logic HIGH L Logic LOW X Don’t Care, ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 3) 0. Input Diode Current ( Output ...
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DC Electrical Characteristics (2.3V Symbol Parameter V HIGH Level Input Voltage IH V LOW Level Input Voltage IL V HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ ...
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AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PHL (REGE 0) PLH t Propagation Delay CLK to O PHL n t (REGE 1) PLH Propagation Delay ...
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AC Loading and Waveforms TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...