SI2107-X-FM SILABS [Silicon Laboratories], SI2107-X-FM Datasheet
SI2107-X-FM
Related parts for SI2107-X-FM
SI2107-X-FM Summary of contents
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... LNB supply solution. Si2109/10 versions include a hardware channel scan accelerator for fast “blindscan”. The Si2107/08/ 09/10 family features new channel detection and acquisition technology: QuickLock for Si2107/08/09/10 and QuickScan for Si2109/10. QuickLock achieves fast channel acquisition and QuickScan, fast channel detection ...
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... Si2107/08/09/10 2 Preliminary Rev. 0.81 ...
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... On-Chip LNB DC-DC Step-Up Controller (Si2108/10 Only 6.9. On-Chip Blindscan Controller: QuickScan (Si2109/10 Only Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10. Ordering Guide1 11. Package Outline: 44-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 12. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Si2107/08/09/10 Preliminary Rev. 0.81 Page 3 ...
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... Permanent damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operations sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The Si2107/08/09/ high-performance RF integrated circuit. Handling and assembly of these devices should only be done at ESD-protected workstations. 4 ...
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... Max gain 3 2 IP3 Min gain L 950 to 2150 MHz LO 100 kHz offset MHz offset N 10 kHz to 1/2 Baud LO Rate At 20 MHz offset t s, Preliminary Rev. 0.81 Si2107/08/09/10 Min Typ Max Unit — 313 — mA — 298 — mA — 292 — mA — 217 — mA 2.3 — ...
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... Si2107/08/09/10 Table 5. Receiver Characteristics Parameter Rf Input Frequency Range Fine Tune Step Size Symbol Rate Range Carrier Offset Correction Range Carrier Lock/Acquisition Times with QuickLock *Note: For signal with C/N = 8.5 dB Pin = –40 dBm, Channel frequency = 1560 MHz. 6 Symbol Test Condition step ...
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... Maximum LNB Supply Current Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise and Fall Time Tone Detector Frequency Capture Range Tone Detector Input Amplitude Note: Specifications based on recommended schematics in Figure 8 and Figure 9. Si2107/08/09/10 Symbol Test Condition Min V 8 LNB_IN 237 VHIGH = 1101 17 ...
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... Si2107/08/09/10 2 Table Bus Characteristics Parameter SCL Clock Frequency Bus Free Time between START and STOP Condition Hold Time (repeated) START Condition. (After this period, the first clock pulse is generated.) LOW Period of SCL Clock HIGH Period of SCL Clock Data Setup Time ...
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... Parallel mode Serial mode (TSSCR = 01) Serial mode (TSSCR = 11) Parallel mode Normal operation Data delayed (TSDD = 1) Clock Delayed (TSCD = 1) Normal operation Data delayed (TSDD = 1) Clock Delayed (TSCD = 1) t cycle t setup t access Preliminary Rev. 0.81 Si2107/08/09/10 Min Typ Max Unit 11.3 — 28 — 8000 ns 5.1 — 6.9 ns 12.0 — ...
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... Si2107/08/09/10 Table 9. MPEG-TS Specifications (Rising Launch, Falling Capture) Parameter Symbol Clock cycle time t cycle Clock low time t clow Clock high time t chigh Hold time t hold Setup time t setup Access time t access L TS_CLK TS_DATA Figure 3. MPEG-TS (Rising Launch, Falling Capture) Timing Diagram ...
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... Input Power (dBm) Figure 4. Eb/No (QEF Operation) vs. Input Power for Si2107/08/09/10 (Typical 27.5 MBaud 7/8 1 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 0.00000001 2 4 Eb/No (dB) Figure 5. BER After Viterbi vs. Eb/No for Si2107/08/09/10 Preliminary Rev. 0.81 Si2107/08/09/10 -40 -20 0 27.5Mbaud 1/2 27.5Mbaud 2/3 27.5Mbaud 3/4 27.5Mbaud 5/6 27.5Mbaud 7 All tests performed with 1550 MHz, –40 dBm input ...
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... Si2107/08/09/10 Figure 6. Phase Noise Performance for Si2107/08/09/10 (Typical) 0.3 0.25 0.2 0.15 0.1 0.05 0 -10 Frequency Offset of Desired Channel (MHz) Figure 7. Frequency Offset vs. Carrier Lock/Acquisition Time for Various Baudrates Using QuickLock (Typical) Preliminary Rev. 0.81 1 Mbaud 2Mbaud 5Mbaud 10Mbaud 20Mbaud 35Mbaud 45Mbaud Test Conditions Pin = –40 dBm ...
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... XTAL1 1 35 REXT XTAL2 2 34 ADDR VDD_XTAL 3 33 VDD_MIX XTOUT 4 32 VDD_BB VDD_PLL33 5 31 VDD_ADC INT/RLK/GPO 6 30 TDET/VSEN TS_ERR 7 29 TGEN/LNB1 TS_VAL 8 28 NC/ISEN TS_SYNC 9 27 DRC/LNB2 SDA 10 26 RESET SCL 11 25 DCS/PWM TS_DATA7 12 24 VDD_DIG18 TS_DATA6 13 23 Preliminary Rev. 0.81 Si2107/08/09/10 13 ...
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... Si2107/08/09/10 14 Si2110 LNB Control Si2110 LNB Control Preliminary Rev. 0.81 ...
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... Si2110 LNB Control Si2110 LNB Control Preliminary Rev. 0.81 Si2107/08/09/10 15 ...
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... Si2107/08/09/10 3. Bill of Materials Table 10. Si2107/08/09/10 Bill of Materials Component C1,C2,C4,C6,C10,C8,C9,C13,C14, C15,C16 C5 C3,C7,C11,C12 C19,C36 TC1 Notes: 1. Transient voltage suppression device should be selected to match the surge requirements of the application. 2. Tuning component values depend on balun selected and layout. Please contact Silicon Laboratories for assistance reviewing layouts and selecting matching components ...
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... R10 R11 R12,R20 R13 R14 R15 R16 R17 Preliminary Rev. 0.81 Si2107/08/09/10 Description 0.47 µ X7R,± 20 X7R, ± 20% 0.22 µ X7R, ± 20% 4.7 µ X7R, ± 20% CMPSH1- ZHCS750TA 750 mA SD0705-330K-R-SL ZXMN3B14 FDN337N FMMT618 MMBT3904 FMMT718 1.3 Ω ...
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... Si2107/08/09/10 Table 12. DiSEqC 2.x LNB Supply Bill of Materials (Si2108/10 Only) Component C17 C30 C31,C35 C32 C33 C34 Q3,Q5, R10 R11 R12,R20 R13 R14 R15 R16 R17 R18 18 Description 1200 pF X7R, ± 20% 47 µ Electrolytic, ± 20% 0.47 µ ...
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... LNB supply regulator circuit. The LNB supply controller utilizes a step-up converter architecture. In case operation with an external regulator is desired, Si2107 and Si2109 can be used; these do not integrate the LNB step-up dc-dc controller. On the other hand, the Si2109 and Si2110 integrate an on-chip “ ...
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... BPSK errors. The Si2107/08/09/10 performs deinterleaving according to DVB-S and DSS standards. 5.3.3. Reed-Solomon Decoder The Si2107/08/09/10 supports RS codes in compliance with DVB-S and DSS specifications. Both standards use a shortened Reed-Solomon code, which can correct up to eight byte errors per information packet. DVB-S utilizes 204 byte codes. DSS utilizes 146 byte codes. ...
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... For each valid DVB-S/DSS channel, the tuning frequency and symbol rate, which can be stored by the host for subsequent tuning, are determined. On Si2107/08 devices, the host needs to provide the channel tuning frequency and symbol rate to the device. 5.5. LNB Signaling Controller ...
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... The TS_ERR output is active during the entire erred TS frame. The polarity of TS_ERR can be programmed to be active high or active low using the TSEP bit. Si2107/08/09/10 All signals on the MPEG-TS output interface can be individually tri-stated using bits TSE_OE, TSV_OE, TSS_OE, TSC_OE, and TSD_OE. ...
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... Interrupts The device is equipped with several sticky interrupt bits to provide precise event tracking and monitoring. Next to interrupts being signaled via the I map, the user can program one of the device terminals Preliminary Rev. 0.81 Si2107/08/09/10 RS1 TS1 (sync) TS2 TS1 (sync) TS2 RS1 ...
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... Message receive timeout Short-circuit detect Over current detect Blindscan done Blindscan data ready Si2107/08/09/10 active high or active low using the interrupt polarity bit, INTP. The interrupt signal type can be configured to be CMOS output or open-drain/source output using the interrupt type bit, INTT. ...
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... Viterbi code rate search (VTF), frame sync search (FSF), and overall receiver acquisition (AQF), 6.4. Tuning Control The Si2107/08/09/10 utilizes a unique two-stage tuning algorithm to provide optimal RF reception. The input signal is first mixed down to a low-IF frequency by a coarse tuning stage and then down to baseband by a fine-tune mixer ...
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... Unlock Unlock f s × ------- - + CFO Unlock Unlock Unlock Figure 15. Fade Recovery Sequence Preliminary Rev. 0.81 Si2107/08/09/10 Calibration LO Tuning Analog AGC Search Done CFO Estimation Done Symbol Timing Loop lock Carrier Frequency Loop lock Viterbi Search (Limited) lock Frame Search lock Receiver locked ...
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... When operating in the finite window mode, the VTERS bit will automatically be cleared when the measurement is complete. The VTERS bit must be cleared manually in the infinite mode to stop the count. Si2107/08/09/10 6.5.3. Reed-Solomon Error Monitor The Reed-Solomon error monitor is capable of counting bit, byte, and uncorrectable packet errors. The error type to be counted is controlled by the Reed-Solomon error type register, RSERT ...
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... If an inversion is detected, data are inverted prior to being output. 6.6. Automatic Gain Control The Si2107/08/09/10 is equipped with the ability to adjust signal levels via an automatic gain control (AGC) loop. This ensures that the noise and linearity characteristics of the signal path are optimized at all times ...
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... BRST_DS, to one. This disables the tone/burst generation as part of the DiSEqC signaling sequence when the device uses “Automatic LNB messaging mode” as described below. Envelope 2.x-compliant Tone Envelope Tone Figure 17. Tone Burst Modulation Preliminary Rev. 0.81 Si2107/08/09/10 100 × TFQ 7:0 + ...
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... The LNB signaling modes are described in the following 1.0 ms sections. 6.7.4.1. Automatic LNB Messaging Mode The Si2107/08/09/10 LNB Signaling Controller can fully manage the generation and sequencing of all LNB commands. The device is configured in this mode by appropriately programming the LNB Messaging mode register, LNBM. To initiate a message sequence, the ...
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... TDET pin. In this mode, the tone direction control bit, TDIR, directly controls the output of the DRC pin. 2nd message Reply to 2nd (reply requested) message > 25ms < 150ms Figure 21. LNB Signaling Sequence Preliminary Rev. 0.81 Si2107/08/09/10 Start of continuous Tone Burst tone (if present) > 15ms > 15ms 31 ...
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... The programming sequence is as follows: 1. Program the frequency range (BS_FMIN, BS_FMAX) and symbol rate range (SRMIN, SRMAX) values over which to perform blindscan. Preliminary Rev. 0.81 Si2107/08/09/10 whereby the minimum and process, any ...
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... Important highly recommended that the registers in Step 2 be programmed with default values provided by Silicon Laboratories. Refer to “AN298: Si2107/08/09/ 10 Application Programming Software”, for the recommended values. The values are documented in the QuickScan section of the application note ...
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... C Control Interface 2 The I C bus interface is provided for configuration and monitoring of all internal registers. The Si2107/08/09/10 supports the 7-bit addressing procedure and is capable of operating at rates up to 400 kbps. Individual data transfers to and from the device are 8-bits. The I consists of two wires: a serial clock line (SCL) and a serial data line (SDA) ...
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... RSER_E MSGPE_E FE_E BSDA_E CEL_I STL_I STU_I CRU_I VTU_I RSER_I MSGPE_I FE_I BSDA_I Receiver Status CEL SRL STL CEF SRF STF Preliminary Rev. 0.81 Si2107/08/09/ REV[3:0] SYSM[2:0] TSCE TSDF TSM TSPG TSSCR[1:0] TSS_OE TSC_OE TSD_OE GPO PSEL[1:0] CRL_E VTL_E FSL_E FSU_E ...
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... Si2107/08/09/10 Name Addr. Acq Ctrl 1 14h AQS ADC SR 15h Coarse Tune 16h Fine Tune L 17h Fine Tune H 18h CE Ctrl 29h CE Offset L 36h CE Offset H 37h CE Err L 38h CE Err H 39h Sym Rate L 3Fh Sym Rate M 40h Sym Rate H 41h CN Ctrl 7Ch ...
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... LNB Supply Controller LNBV LNBCT LNBB MMSG TT TR TFQ[7:0] FF MSGPE MSGR MSGTO FIFO1[7:0] FIFO2[7:0] FIFO3[7:0] FIFO4[7:0] FIFO5[7:0] FIFO6[7:0] VLOW[3:0] IMAX[1:0] VMON[7:0] LNB_EN Preliminary Rev. 0.81 Si2107/08/09/ AGCO[3:0] AGC1[3:0] AGC3[3:0] DAGC2W[1:0] DAGC2TDIS MSGL[2:0] BRST_DS TFS MSGRL[2:0] VHIGH[3:0] SLOT[1:0] OLOT[1:0] COMP LNBMD SCD OCD ...
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... Si2107/08/09/10 Name Addr. Host Ctrl 1Ch RS Est L 31h RS Est M 32h RS Est H 33h SR Est Ctrl 2 3Ah SR Max 42h SR Min 43h BS Ctrl 80h BS_ START BS MinFreq L 81h BS MinFreq M 82h BS MinFreq H 83h BS MaxFreq L 84h BS MaxFreq M 85h BS MaxFreq H 86h BS CoarseFreq 89h BS FineFreq L 8Ah ...
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... Bit Name 7:6 Reserved 5 INC_DS 4:3 MOD[1:0] 2:0 SYSM[2: Function Device ID Si2110 1h = Si2109 2h = Si2108 3h = Si2107 Revision. Current revision = INC_DS MOD[1:0] Function Program as shown above Automatic Address Increment Disable Enabled (default Disabled Modulation Selection BPSK Demodulation 01 = QPSK Demodulation (default Reserved 11 = Reserved System Mode ...
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... Si2107/08/09/10 Register 02h. Transport Stream Control 1 Bit D7 D6 Name TSEP TSVP Bit Name 7 TSEP 6 TSVP 5 TSSP 4 TSSL 3 TSCM 2 TSCE 1 TSDF 0 TSM TSSP TSSL TSCM Function Transport Stream Error Polarity Active high (default Active low Transport Stream Valid Polarity Active high (default Active low Transport Stream Sync Polarity ...
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... Transport Stream Serial Clock Rate 80–88.5 MHz (default 76.8–82.8 MHz 10 = 54.8–59.2 MHz 11 = 34.9–37.7 MHz The user should select a setting such that the corresponding minimum clock output frequency is higher than the expected output bit rate. Preliminary Rev. 0.81 Si2107/08/09/ TSPG TSSCR[1:0] Function 41 ...
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... Si2107/08/09/10 Register 04h. Pin Control Bit INT_EN INTT Name Bit Name 7 INT_EN 6 INTT 5 INTP 4 TSE_OE 3 TSV_OE 2 TSS_OE 1 TSC_OE 0 TSD_OE INTP TSE_OE TSV_OE Interrupt Pin Enable Disabled (default Enabled Interrupt Pin Type CMOS (default Open drain/source Interrupt Polarity Active low (default Active high Transport Stream Error Output Enable ...
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... Descrambler Bypass Normal operation (default Bypass Note: This bit is ignored in DSS mode; the descrambler is automatically bypassed. Reed-Solomon Bypass Normal operation (default Bypass Deinterleaver Bypass Normal operation (default Bypass Program as shown above. Preliminary Rev. 0.81 Si2107/08/09/ GPO PSEL[1:0] Function ...
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... Si2107/08/09/10 Register 07h. Interrupt Enable 1 Bit D7 D6 Name RCVL_E AGCL_E Bit Name 7 RCVL_E 6 AGCL_E 5 CEL_E 4 Reserved 3 STL_E 2 CRL_E 1 VTL_E 0 FSL_E CEL_E 0 STL_E Function Receiver Lock Interrupt Enable Disabled (default Enabled AGC Lock Interrupt Enable Disabled (default Enabled Carrier Estimator Lock Interrupt Enable. ...
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... Enabled Carrier Recovery Unlock Interrupt Enable Disabled (default Enabled Viterbi Search Unlock Interrupt Enable Disabled (default Enabled Frame Sync Unlock Interrupt Enable Disabled (default Enabled Program as shown above. Acquisition Fail Interrupt Enable Disabled (default Enabled Preliminary Rev. 0.81 Si2107/08/09/ FSU_E 0 AQF_E 45 ...
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... Si2107/08/09/10 Register 09h. Interrupt Enable 3 Bit D7 D6 Name CN_E VTER_E RSER_E Bit Name 7 CN_E 6 VTER_E 5 RSER_E 4 MSGPE_E 3 FE_E 2 FF_E 1 MSGR_E 0 MSGTO_E MSGPE_E FE_E C/N Estimator Interrupt Enable Disabled (default Enabled Viterbi BER Interrupt Enable Disabled (default Enabled Reed-Solomon Error Measurement Interrupt Enable. ...
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... Blindscan Done Interrupt Enable Disabled (default Enabled Blindscan Data Ready Interrupt Enable Disabled (default Enabled Program as shown above. Short Circuit Detect Interrupt Enable Disabled (default Enabled Over Current Detect Interrupt Enable Disabled (default Enabled Preliminary Rev. 0.81 Si2107/08/09/ SCD_E OCD_E 0 SCD_E OCD_E Function 47 ...
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... Si2107/08/09/10 Register 0Bh. Interrupt Status 1 Bit D7 D6 Name RCVL_I AGCL_I Bit Name 7 RCVL_I 6 AGCL_I 5 CEL_I 4 Reserved 3 STL_I 2 CRL_I 1 VTL_I 0 FSL_I CEL_I 0 STL_I Function Receiver Lock Interrupt Disabled (default Enabled AGC Lock Interrupt Disabled (default Enabled Carrier Estimator Lock Interrupt. ...
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... Carrier Recovery Unlock Interrupt Normal operation (default Event recorded Viterbi Search Unlock Interrupt Normal operation (default Event recorded Frame Sync Unlock Interrupt Normal operation (default Event recorded Program as shown above. Acquisition Fail Interrupt Normal operation (default Event recorded Preliminary Rev. 0.81 Si2107/08/09/ FSU_I 0 AQF_I 49 ...
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... Si2107/08/09/10 Register 0Dh. Interrupt Status 3 Bit D7 D6 Name CN_I VTER_I Bit Name 7 CN_I 6 VTER_I 5 RSER_I 4 MSGPE_I 3 FE_I 2 FF_I 1 MSGR_I 0 MSGTO_I RSER_I MSGPE_I FE_I C/N Estimator Interrupt Normal operation (default Event recorded Viterbi BER Interrupt Normal operation (default Event recorded Reed-Solomon Error Measurement Complete Interrupt. ...
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... Blindscan data can be read from registers: BS_CTF, BS_FTF, CFER, SREST, BS_ADCSR. Program as shown above. Short Circuit Detect Interrupt Normal operation (default Event recorded Over Current Detect Interrupt Normal operation (default Event recorded Preliminary Rev. 0.81 Si2107/08/09/ SCD_I OCD_I 0 SCD_I OCD_I ...
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... Si2107/08/09/10 Register 0Fh. Lock Status 1 Bit AGCL Name Bit Name 7 Reserved 6 AGCL 5 CEL 4 SRL 3 STL 2 CRL 1 VTL 0 FSL CEL SRL STL Function Program as shown above. AGC Lock Status Pending (default Complete Carrier Estimation Status Pending (default Complete Symbol Rate Estimation Status. ...
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... Locked Program as shown above. Blindscan Data Ready (LSA stage Normal operation (default Raw carrier and symbol rate ready for readout by host. Blindscan Done Normal operation (default Blindscan sequence complete over the specified frequency range. Preliminary Rev. 0.81 Si2107/08/09/ BSDA ...
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... Si2107/08/09/10 Register 11h. Acquisition Status Bit D7 D6 Name AQF AGCF Bit Name 7 AQF 6 AGCF 5 CEF 4 SRF 3 STF 2 CRF 1 VTF 0 FSF CEF SRF STF Function Receiver Acquisition Status Normal operation (default Acquisition failed AGC Search Status Normal operation (default Gain control limit reached Carrier Estimation Search Status ...
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... ADC Sampling Rate ADCSR x 1 MHz s Default: C8h (200 MHz CTF[7:0] Function Coarse Tune Frequency. Calculation of the coarse tune value is determined by the reference software driver CTF x 10 MHz coarse Default: 00h Preliminary Rev. 0.81 Si2107/08/09/ ...
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... Si2107/08/09/10 Register 17h. Fine Tune Frequency L Bit D7 D6 Name Bit Name 7:0 FTF[7:0] Register 18h. Fine Tune Frequency H Bit D7 D6 Name 0 Bit Name 7 Reserved 6:0 FTF[14: FTF[7:0] Function Fine Tune Frequency (Low Byte fine where FTF is stored complement value. Calculation of the fine tune value is determined by the reference soft- ware driver ...
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... D4 0 AGCW[1:0] Program as shown above. AGC Measurement Window. Acquisition Tracking 00 = 1024 (default) 65536 samples (default 2048 131072 samples 10 = 4096 262144 samples 11 = 8192 524288 samples Program as shown above. Preliminary Rev. 0.81 Si2107/08/09/ CTF_CTRL_ FTF_CTRL_ HOST HOST HOST Function Function ...
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... Si2107/08/09/10 Register 24h. AGC Control 2 Bit D7 D6 Name AGCTR[3:0] Bit Name 7:4 AGCTR[3:0] 3:0 AGCO[3:0] Register 25h. Analog AGC 1–2 Gain Bit D7 D6 Name AGC2[3:0] Bit Name 7:4 AGC2[3:0] 3:0 AGC1[3:0] Register 26h. Analog AGC 3–4 Gain Bit D7 D6 Name AGC4[3:0] Bit Name 7:4 AGC4[3:0] 3:0 AGC3[3:0] ...
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... AGC power level to this value. Default: 20h AGCPWR[6:0] Function Program as shown above. AGC Power Level. Represents the measured input power level after the ADC in rms format. The measurement window is set by AGCW. This register saturates at full scale. Default: 00h. Preliminary Rev. 0.81 Si2107/08/09/ ...
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... Si2107/08/09/10 Register 29h. Carrier Estimation Control D7 D6 Bit 0 0 Name Bit Name 7:3 Reserved 2:0 CESR[2:0] Register 31h. Symbol Rate Estimator Register L (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 SREST[7:0] Register 32h. Symbol Rate Estimator Register M (Si2109 and Si2110 only) Bit ...
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... Carrier Frequency Offset (Low Byte). Designed to store a residual carrier frequency offset for future acquisi- tions. Used during carrier offset estimation to adjust the center fre- quency. Search center frequency Note: CFO is a 16-bit two’s complement number. Default: 00h Preliminary Rev. 0.81 Si2107/08/09/ × ...
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... Si2107/08/09/10 Register 37h. Carrier Estimator Offset Bit Name Bit Name 7:0 CFO[15:8] Register 38h. Carrier Frequency Offset Error Bit Name Bit Name 7:0 CFER[7:0] Register 39h. Carrier Frequency Offset Error H Bit D7 D6 Name Bit Name 7:0 CFER[15: CFO[15:8] Function Carrier Frequency Offset (High Byte). ...
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... Enable the SRE to check for false symbol rate alarms Default: 01h SR[7:0] Function Symbol Rate (Low Byte). Symbol rate Sampling_rate is the ADC sampling rate as calculated from BS_ADCSR. Default: 00h SR[15:8] Function Symbol Rate (Mid Byte). See register 3Fh. Preliminary Rev. 0.81 Si2107/08/09/10 D0 FALSE_ALARM_PROC_EN × ------- - = ...
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... Si2107/08/09/10 Register 41h. Symbol Rate H Bit D7 D6 Name Bit Name 7:0 SR[23:16] Register 42h. Symbol Rate Maximum (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 SRMAX[7:0] Register 43h. Symbol Rate Minimum (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 SRMIN[7: ...
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... Do not update gain value Host-controlled DAGC1 Enable host control of holding of gain control internal to chip (default host control via registers DAGC1HOLD and DAGC1T Program as shown above DAGC1[7:0] Gain of digital AGC 1 (low-byte). Default: 00h Preliminary Rev. 0.81 Si2107/08/09/ DAGC1HOST 0 Function Function 65 ...
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... Si2107/08/09/10 Register 77h. Digital AGC 1 Gain H Bit D7 D6 Name Bit Name 7:0 DAGC1[15:8] Register 78h. Digital AGC 2 Control Bit D7 D6 Name Reserved Bit Name 7 Reserved 6:3 DAGC2[3:0] 2:1 DAGC2W[1:0] 0 DAGC2TDIS Register 79h. Digital AGC 2 Threshold Bit D7 D6 Name Bit Name 7:0 DAGC2T[7: DAGC1[15:8] Function Gain of digital AGC 1 (high-byte) ...
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... CNL. This bit is automatically cleared to zero when the mea- surement period elapses. Program as shown above. C/N Estimator Mode Finite window 1 = Infinite window (default) C/N Measurement Window 1024 samples 01 = 4096 samples (default 16384 samples 11 = 65536 samples Preliminary Rev. 0.81 Si2107/08/09/ CNM CNW[1:0] ...
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... Si2107/08/09/10 Register 7Dh. C/N Estimator Threshold0 Bit D7 D6 Name Bit Name 7:0 CNET[7:0] Register 7Eh. C/N Estimator Level L Bit D7 D6 Name Bit Name 7:0 CNL[7:0] Register 7Fh. C/N Estimator Level H Bit D7 D6 Name Bit Name 7:0 CNL[15: CNET[7:0] Function C/N Estimator Threshold. This value defines a noise threshold for the C/N estimator. ...
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... Program as shown above. Carrier Offset Estimation Selection Mode Legacy Mode (default QuickLock BS_FMIN[7:0] Function Minimum Frequency (MHz) ----------------------------------------------------------------------- - BS_FMIN = BS_ADCSR (MHz) Preliminary Rev. 0.81 Si2107/08/09/ COESM × ...
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... Si2107/08/09/10 Register 82h. Blindscan Controller Minimum Frequency Register M (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 BS_FMIN[15:8] See register 81h. Default: 08h Register 83h. Blindscan Controller Minimum Frequency Register H (Si2109 and Si2110 only) Bit D7 D6 Name 0 0 Bit Name 7:2 Reserved Program as shown above ...
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... D7 D6 Bit Name Bit Name 7:0 BS_FTF[7:0] Fine frequency of identified channel, low byte. Fine frequency = BS_Fs/16384 x BS_FTF Default: 00h BS_FMAX[15:8] Function Function BS_CTF[7:0] Function BS_FTF[7:0] Function Preliminary Rev. 0.81 Si2107/08/09/ BS_FMAX[17:16 ...
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... Si2107/08/09/10 Register 8Bh. Blindscan Controller Fine Tuning Frequency Register H (Si2109 and Si2110 only) Bit D7 D6 Name 0 Bit Name 7 Reserved Program as shown above. 6:0 BS_FTF[14:8] Fine frequency of identified channel, high byte. See register 8Ah. Default: 00h Register 8Ch. Blindscan Controller ADC Sampling Rate Register (Si2109 and Si2110 only) ...
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... QuickLock/QuickScan operation BW_2dB Function BW_3dB Function Threshold used to determine 3 dB bandwidth for a detected channel. Refer to Silicon Laboratories application note AN298 for recommended default values for QuickLock/QuickScan operation. Preliminary Rev. 0.81 Si2107/08/09/ ...
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... Si2107/08/09/10 Register 93h. Inband Power Threshold Register (Si2109 and Si2110 only) Bit D7 D6 Name Bit Name 7:0 INBAND_ Threshold for determining the drop in power in a channel as the LSA scans a THRESHOLD[7:0] detected channel to determine the channel bandwidth. Refer to Silicon Laboratories application note AN298 for recommended default val- ues for QuickLock/QuickScan operation ...
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... Undefined Program as shown above. Viterbi Constellation Rotation Phase Status Not rotated (default Rotated by 90 degrees Viterbi I/Q Swap Status Not swapped (default Swapped Preliminary Rev. 0.81 Si2107/08/09/ VTERM VTERW[1: VTPS VTIQS 0 ...
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... Si2107/08/09/10 Register ABh. Viterbi BER Count L Bit D7 D6 Name Bit Name 7:0 VTERC[7:0] Register ACh. Viterbi BER Count H Bit D7 D6 Name Bit Name 7:0 VTERC[15: VTERC[7:0] Function Viterbi BER Counter (Low Byte). Stores the number of the Viterbi bit errors detected within the specified measurement window ...
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... Uncorrected packets 11 = PRBS errors RSERC[7:0] Function Reed-Solomon Error Counter (Low Byte). Stores the number PRBS errors detected within the specified window. This register saturates when it reaches the limit of its range. Default: 00h Preliminary Rev. 0.81 Si2107/08/09/ RSERW RSERT[1: ...
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... Si2107/08/09/10 Register B2h. Reed-Solomon Error Monitor Count H Bit D7 D6 Name Bit Name 7:0 RSERC[15:8] Register B3h. Descrambler Control Bit D7 D6 Name 0 0 Bit Name 7:2 Reserved 1 DST_DS 0 DSO_DS RSERC[15:8] Function Reed-Solomon Error Counter (High Byte). See Register B1h Function Program as shown above ...
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... This signals the number of bytes at the start packet that are con- sidered TS header, and that are not occupied by PRBS data in PRBS test mode. DVB-S mode DSS mode (Default Preliminary Rev. 0.81 Si2107/08/09/ PRBS_HEADER_SIZE[1: ...
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... Longer than six bytes. Notes: 1. When message length is set to one byte, tone burst modulation is used. When message length is set to two or more bytes, DiSEqC modulation is used. 2. Not available in manual LNB mode Si2107/9 LNBCT LNBB MMSG Si2108/10 LNBCT LNBB MMSG Function Preliminary Rev ...
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... Note: This bit is only active in manual LNB mode. Tone Receive. Detects input on TDET pin tone or low signal detected (default Tone or high signal detected Note: This bit is only active in manual LNB mode. Program as shown above. Preliminary Rev. 0.81 Si2107/08/09/ BRST_DS TFS 0 D2 ...
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... Si2107/08/09/10 Register C3h. LNB Control 4 Bit D7 D6 Name Bit Name 7 TFQ[7: TFQ[7:0] Function LNB Tone Frequency Control. Used to set the frequency of the LNB tone according to the following equation: Frequency = 100 MHz/[32 x (TFQ+1)] 00000000–01111011 = Reserved 01111100–10011011 = valid range 10011100– ...
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... Message reply not received within 150 ms Received Message Length. 000 = No message (default) 001 = One byte 010 = Two bytes 011 = Three bytes 100 = Four bytes 101 = Five bytes 110 = Six bytes 111 = Longer than six bytes Preliminary Rev. 0.81 Si2107/08/09/ MSGRL[2:0] Function 83 ...
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... Si2107/08/09/10 Register C5-CAh. Message FIFO 1–6 Bit D7 D6 Name Bit Name 7:0 FIFO1–6[7:0] Register CBh. LNB Supply Control 1 (Si2108 and Si2110 only) Bit D7 D6 Name VLOW[3:0] Bit Name 7:4 VLOW[3:0] 3:0 VHIGH[3: FIF0x[7:0] Function Message FIFO. Contains message to be transmitted or message received ...
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... Overcurrent Lockout Time 2 3. 5.0 ms (default 7 VMON[7:0] Function LNB Voltage Monitor (read only). LNB output voltage = VMON x 0.0625 + 6 V Preliminary Rev. 0.81 Si2107/08/09/ OLOT[1: ...
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... Si2107/08/09/10 Register CEh. LNB Supply Control 4 (Si2108 and Si2110 only) Bit D7 D6 Name LNBL 0 Bit Name 7 LNBL 6:4 Reserved 3 LNB_EN 2 COMP 1 Reserved 0 LNBMD Register CFh. LNB Supply Status (Si2108 and Si2110 only) Bit D7 D6 Name 0 0 Bit Name 7:2 Reserved 1 SCD 0 OCD 86 D5 ...
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... TGEN—Outputs tone or tone envelope. Current Sense (Si2108/10 only). 9 ISEN I Monitors current of LNB supply circuit. When LNB supply circuit is not populated or when using Si2107/09, leave pin unconnected. LNB Control 2/Direction Control. LNB2 (Si2108/10 only)—required connection to LNB supply circuit. 10 LNB2/DRC O DRC—Outputs signal to indicate message transmission (HIGH) or reception (LOW) ...
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... Si2107/08/09/10 Pin # Name I/O PWM/DC Voltage Select. PWM (Si2108/10 only)—Connected to gate of power MOSFET for LNB supply cir- 12 PWM/DCS O cuit. DCS—Outputs signal to indicate 18 V (HIGH (LOW) LNB supply voltage selection. Supply voltage. 13 VDD_DIG18 I Digital power supply. Connect to 1.8 V. 14–17, Transport Stream Data Bus. ...
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... Pb-free and RoHS Compliant Si2108-X-FM Satellite receiver for DVB-S/DSS with step-up dc-dc controller, Pb- free and RoHS Compliant Si2107-X-FM Satellite receiver for DVB-S/DSS, Pb-free and RoHS Compliant Notes: 1. “X” denotes product revision. 2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. ...
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... Si2107/08/09/10 11. Package Outline: 44-pin QFN Figure 23 illustrates the package details for the Si2110. Table 20 lists the values for the dimensions shown in the illustration. Table 20. Package Diagram Dimensions Millimeters Dimension Min Nom A 0.80 0.90 A1 0.00 0.02 b 0.18 0.25 D 6.00 BSC. D2 2.70 2.80 e 0.50 BSC. E 8.00 BSC. Notes: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. ...
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... PCB Land Pattern Figure 24. PCB Land Pattern Preliminary Rev. 0.81 Si2107/08/09/10 91 ...
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... Si2107/08/09/10 Table 21. PCB Land Pattern Dimensions Dimension Notes - General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0 ...
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... On-Chip Blindscan Controller: QuickScan (Si2109/10 Only)" on page 32. Added graphs of performance illustrating typical performance. Figure 4, “Eb/No (QEF Operation) vs. Input Power for Si2107/08/09/10 (Typical 27.5 MBaud 7/8,” on page 11. Figure 5, “BER After Viterbi vs. Eb/No for Si2107/08/09/ 10,” on page 11. Figure 6, “Phase Noise Performance for Si2107/08/09/ 10 (Typical),” ...
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... Si2107/08/09/ ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: DBSinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...