ZL50418GKC ZARLINK [Zarlink Semiconductor Inc], ZL50418GKC Datasheet
ZL50418GKC
Related parts for ZL50418GKC
ZL50418GKC Summary of contents
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Features • Integrated Single-Chip 10/100/1000 Mbps Ethernet Switch • 16 10/100 Mbps Autosensing, Fast Ethernet Ports with RMII or Serial Interface (7WS). Each port can independently use one of the two interfaces • 2 Gigabit Ports with GMII, PCS and ...
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Traffic Classification • 4 transmission priorities for Fast Ethernet ports with 2 dropping levels • Classification based on: - Port based priority - VLAN Priority field in VLAN tagged frame - DS/TOS field in IP packet - UDP/TCP logical ...
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Description The ZL50418 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 16 ports at 10/100 Mbps, 2 ports at 1000 Mbps and a CPU interface for managed and unmanaged switch applications. The ...
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Block Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Runts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PVROUTE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INTP_MASK6 – Interrupt Mask for MAC Port 12, ...
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USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority . . . . . . . . . . . . . 98 14.9.40.4 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority . . . . ...
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Encapsulated view in unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - ZL50418 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block Functionality 1.1 Frame Data Buffer (FDB) Interfaces The FDB interface supports pipelined synchronous burst SRAM (SBRAM) memory at 100 MHz. To ensure a non-blocking switch, two memory domains are required. Each domain has a 64 bit wide memory ...
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MAC Module (RMAC) The 10/100 Media Access Control module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). The ZL50418 has two interfaces, RMII or Serial (only for 10 ...
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System Configuration 2.1 Management and Configuration Two modes are supported in the ZL50418: managed and unmanaged. In managed mode, the ZL50418 uses bit CPU interface very similar to the Industry Standard Architecture (ISA) specification. In ...
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Similarly, to read the value in the register addressed by the two index registers, the “configure data” register can now simply be read. In summary, access to the many internal registers is carried out simply by directly accessing only ...
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Learn MAC address • Delete MAC address • Delete IP Multicast address • New VLAN port • Age out VLAN port • Response to search MAC address request from CPU • Response to search IP Multicast address request from ...
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If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let the master generate the Stop condition. 2.4.5 Data After the first byte containing the address, all bytes that follow ...
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Write Command STROBE ... A0 A1 START ADDRESS 2.5.2 Read Command STROBE START ADDRESS AUTOFD- All registers in ZL50418 can be modified through this synchronous serial interface. 3.0 ZL50418 Data Forwarding Protocol 3.1 ...
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If the frame is not dropped then the TxQ manager links the frame’s FCB to the correct per-port-per-class TxQ. Unicast TxQ’s are linked lists of transmission jobs, represented by their associated frames’ FCB’s. There is one linked ...
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Memory Interface 4.1 Overview The ZL50418 provides two 64-bit-wide SRAM banks, SRAM Bank A and SRAM Bank B with a 64-bit bus connected to each. Each DMA can read and write from both bank A and bank B. The ...
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Memory Requirements To speed up searching and decrease memory latency, the external MAC address database is duplicated in both memory banks. To support 64 K MAC address memory is required. When VLAN support is enabled, 512 entries ...
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Search Engine 5.1 Search Engine Overview The ZL50418 search engine is optimized for high throughput searching, with enhanced features to support • MAC addresses • 255 VLAN and IP Multicast groups • 3 ...
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Search, Learning, and Aging 5.3.1 MAC Search The search block performs source MAC address and destination MAC address (or destination IP address for IP multicast) searching indicated earlier match is not found, then the next ...
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VIX7 VIX6 … … … … VIX4095 VIX4094 VIX4093 Each VIX represents the mapping result from the associated VLAN ID (VLANID = 0x004 is mapped to VIX4). Unused VLAN ID’s have their corresponding VIX programmed to hexadecimal 00. Used VLAN ...
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Quality of Service Quality of Service (QoS) refers to the ability of a network to provide better service to selected network traffic over various technologies. Primary goals of QoS include dedicated bandwidth, controlled jitter and latency (required by some ...
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Priority Classification Rule Figure 8 on page 27 shows the ZL50418 priority classification rule. Use Default Port Settings No IP Yes 5.7 Port and Tag Based VLAN The ZL50418 supports two models for determining and controlling how a packet ...
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For example, in the above table a 1 denotes that an outgoing port is eligible to receive a packet from an incoming port (zero) denotes that an outgoing port is not eligible to receive a packet from an ...
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M (SRAM) ZL50415 X ZL50416 X ZL50417 ZL50418 Table 6 - Options for Memory Configuration BANK A (1M One Layer) Data LA_D[63:32] Data LA_D[31:0] SRAM Memory 128 K 32 bits Address LA_A[19:3] Bootstraps: TSTOUT7 = Open, TSTOUT13 = Open, ...
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BANK A (2M Two Layers) Data LA_D[63:32] Data LA_D[31:0] SRAM Memory 128 K 32 bits SRAM Memory 128 K 32 bits Address LA_A[19:3] Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Pull Down, TSTOUT4 = Open Figure 10 - Memory Configuration ...
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Frame Engine 6.1 Data Forwarding Summary When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. Data is moved in 8-byte granules in conjunction with the scheme ...
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TxQ Manager First, the TxQ manager checks the per-class queue status and global reserved resource situation and using this information makes the frame dropping decision after receiving a switch response. If the decision is not to drop, the TxQ ...
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Total Assured Bandwidth (user Goals Middle transmission 37.5 Mbps priority, P2 Low transmission 12.5 Mbps priority, P1 Total 100 Mbps A class is capable of offering traffic that exceeds the contracted bandwidth. A well-behaved class offers traffic at a rate ...
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QOSC32 [7:6]_CREDIT_C20 QOSC36 [7:6]_CREDIT_C30 Delay Bound Op1 (default) SP Op2 SP Op3 WFQ Op4 Table 8 - Four QoS Configurations for a 10/100 Mbps Port QOSC40 [7:6] and QOSC48 [7:6] select these modes for the first and second gigabit ports, ...
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As a result we assure latency bounds for all admitted frames with high confidence, even in the presence of system-wide congestion. Our algorithm identifies misbehaving classes and intelligently discards frames at no detriment to well-behaved classes. Our algorithm also ...
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For example, if the setting is 16, then the average rate for shaped traffic is 16/64 * 1000 Mbps = 250 Mbps consequence of the above settings ...
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WRED Drop Threshold Management Support To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified parameters. The following table summarizes the behavior of the WRED logic (kilobytes) P3 Level 1 N ≥ ...
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The following registers define the size of each section of the Frame data Buffer: • PR100- Port Reservation for 10/100 Ports • PRG- Port Reservation for Giga Ports • SFCB- Share FCB Size • C2RS- Class 2 Reserve Size • ...
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While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. When a source port receives an Ethernet flow control signal, all microflows originating at that port, well-behaved or not, are ...
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Mapping to IETF Diffserv Classes The mapping between priority classes discussed in this chapter and elsewhere is shown below IETF NM EF Table 10 - Mapping between ZL50418 and IETF Diffserv Classes for Gigabit Ports As ...
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Port Trunking 8.1 Features and Restrictions A port group (i.e., trunk) can include physical ports, but when using stack all of the ports in a group must be in the same ZL50418. The two Gigabit ports ...
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Table 13 - Select via trunk0_mode register Group 1 Table 14 - Select via trunk1_mode register Group 2 In unmanaged mode, the trunks are individually enabled/disabled by controlling pin trunk0,1,2. 9.0 Port Mirroring 9.1 Port Mirroring Features The received or ...
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TBI Interface 10.1 TBI Connection The TBI interface can be used for 1000Mbps fiber operation. In this mode, the ZL50418 is connected to the Serdes as shown in Figure 14. There are two TBI interfaces in the ZL50418 devices. ...
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GPSI (7WS) Interface 11.1 GPSI connection The 10/100 RMII ethernet port can function in GPSI (7WS) mode when the corresponding TXEN pin is strapped low with pull down resistor. In this mode, the TXD[0], TXD[1], RXD[0] ...
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SCAN LINK and SCAN COL interface An external CPLD logic is required to take the link signals and collision signals from the GPSI PHYS and shift them into the switch device. The switch device will drive out a signature ...
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When the LED_SYN pulse is asserted, the LED interface will present 256 LED clock cycles with the clock cycles providing information for the following ports. • Port 0 (10/100): cycles #0 to cycle #7 • Port 1 (10/100): cycles#8 to ...
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Hardware Statistics Counter 13.1 Hardware Statistics Counters List ZL50418 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these counters through the CPU interface. All hardware counters are rollover counters. When a counter ...
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B[29] F-U Late Collision B[30] Link Status Change B[31] Current link status Notation: X-Y X: Address in the contain memory Y: Size and bits for the counter d: D Word counter L: 24 bits counter bit [23: bits ...
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FCSErrors Counts number of valid frames received with bad FCS. Frame size: No framing error No collisions 13.2.1.4 AlignmentErrors Counts number of valid frames received with bad alignment (not byte-aligned). Frame size: No framing error No collisions 13.2.1.5 FrameTooLongs ...
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Runts Counts number of frames received with size under 64 bytes, but greater than the length of a short event. Frame size: FCS error: Framing error: No collisions 13.2.1.8 Collisions Counts number of collision events. Frame size: 13.2.1.9 LateEvents ...
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IEEE – 802.1 Bridge Management (RFC 1286) 13.3.1 Event Counters 13.3.1.1 InFrames Counts number of frames received by this port or segment. Note: A frame received by this port is only counted by this counter if and only if ...
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CRCAlignErrors Frame size: > 64 bytes, No collisions: Counts number of frames received with FCS or alignment errors 13.4.1.6 UndersizePkts Counts number of frames received with size less than 64 bytes. Frame size: < 64 bytes, No FCS error ...
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Collisions Counts number of collision events detected. Only a best estimate since collisions can only be detected while in transmit mode, but not while in receive mode. Frame size: 13.4.1.11 Packet Count for Different Size Groups Six different size ...
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Register Definition 14.1 ZL50418 Register Description Register Description 0. ETHERNET Port Control Registers Substitute [N] with Port number (0..F,18..1A) ECR1P”N” Port Control Register 1 for Port N ECR2P”N” Port Control Register 2 for Port N GGC Extra GIGA bit ...
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Register Description TRUNK1_ HASH0 Trunk Group 1 Hash 0 Destination Port TRUNK1_ HASH1 Trunk Group 1 Hash 1 Destination Port TRUNK1_ HASH2 Trunk Group 1 Hash 2 Destination Port TRUNK1_ HASH3 Trunk Group 1 Hash 3 Destination Port TRUNK2_ MODE ...
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Register Description Multicast_ Multicast hash result 3 mask byte HASH3-0 0 Multicast_ Multicast hash result 3 mask byte HASH3-1 1 Multicast_ Multicast hash result 3 mask byte HASH3-2 2 Multicast_ Multicast hash result 3 mask byte HASH3 CPU ...
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Register Description AVPML VLAN Priority Map Low AVPMM VLAN Priority Map Middle AVPMH VLAN Priority Map High TOSPML TOS Priority Map Low TOSPMM TOS Priority Map Middle TOSPMH TOS Priority Map High AVDM VLAN Discard Map TOSDML TOS Discard Map ...
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Register Description USER_ User Define Logical Port “N” Low PORT”N”_LOW (N=0-7) USER_ User Define Logical Port “N” High PORT”N”_HIGH USER_ User Define Logic Port 1 and 0 PORT1:0_ Priority PRIORITY USER_ User Define Logic Port 3 and 2 PORT3:2_ Priority ...
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Register Description MIIC0 MII Command Register 0 MIIC1 MII Command Register 1 MIIC2 MII Command Register 2 MIIC3 MII Command Register 3 MIID0 MII Data Register 0 MIID1 MII Data Register 1 LED LED Control Register SUM EEPROM Checksum Register ...
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Directly Accessed Registers 14.2.1 INDEX_REG0 • Address bits [7:0] for indirectly accessed register addresses • Address = 0 (write only) 14.2.2 INDEX_REG1 (only needed for 8-bit mode) • Address bits [15:8] for indirectly accessed register addresses • Address = ...
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Bit [5]: • Set this bit to re-start the data that is sent from the CPU to Receive FIFO (re-align). This feature can be used for software debug. For normal operation must be '0'. Bit [6]: • Do not use. ...
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Control Command Frame Buffer1 Access Register • Address = 6 (read/write) • When CPU writes to this register, data is written to the Control Command Frame Receive Buffer • When CPU reads this register, data is read from the ...
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Bit [4: – Automatic Enable Auto Neg. - This enables hardware state machine for auto-negotiation Limited Disable auto Neg. This disables hardware for speed auto-negotiation. Hardware Poll MII for link status Link ...
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Bit [7:6] • Security Enable (Default 00). The ZL50418 checks the incoming data for one of the following conditions the source MAC address of the incoming packet is in the MAC table and is defined as secure address ...
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Bit [5]: • GIGA port B use MII interface (10/100 Gigabit port operates at 1000 mode (default Gigabit port operates at 10/100 mode Bit [6]: • Reserved - Must be zero Bit [7]: • GIGA ...
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PVMAP00_1 – Port 00 Configuration Register Address h53, CPU Address:h103 Accessed by CPU, serial interface and I In Port based VLAN Mode Bit [7:0]: In Tag based VLAN Mode 7 Unitag Port Priority Bit [3:0]: ...
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Bit [6]: Default Discard priority. Used when Bit[7]=1 (Default Discard Priority Level 0 (Lowest Discard Priority Level 1(Highest) Bit [7]: Enable Fix Priority ( Default Disable fix priority. All ...
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Port Configuration Registers 2 PVMAP01_0,1 Address h39,54,8A; CPU Address:h106, 107, 109 2 PVMAP02_0,1 Address h3A, 55,8B; CPU Address:h10A, 10B, 10D 2 PVMAP03_0,1 Address h3B,56,8C; CPU Address:h10E, 10F, 111 2 PVMAP04_0,1 Address ...
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Bit [3]: • Disable Reset PCS (Default = Enable reset PCS. PCS FIFO will be reset when received a PCS symbol error Disable reset PCS Bit [4]: • Support MAC address 0 (Default = 0) ...
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PVROUTE1 CPU Address:h172 Accessed by CPU, serial interface (R/W) Bit [0]: • VLAN Index 8’hC8 has router group and the router group is VLAN Index 8’h48 Bit [1]: • VLAN Index 8’hC9 has router group and the router group ...
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Bit [6]: • VLAN Index 8’hDE has router group and the router group is VLAN Index 8’h5E Bit [7]: • VLAN Index 8’hDF has router group and the router group is VLAN Index 8’h5F 14.5.6 PVROUTE4 CPU Address:h175 Accessed by ...
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Bit [3]: • VLAN Index 8’hF3 has router group and the router group is VLAN Index 8’h73 Bit [4]: • VLAN Index 8’hF4 has router group and the router group is VLAN Index 8’h74 Bit [5]: • VLAN Index 8’hF5 ...
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TRUNK0_M, and TRUNK0_L provide a trunk map for trunk0. If ports 0 and 2 are to be trunked together, bit 0 and bit 2 of TRUNK0_L are set to 1. All others are clear at “0” to indicate that they ...
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TRUNK0_HASH1 – Trunk group 0 hash result 1 destination port number CPU Address:h205 Accessed by CPU, serial interface (R/W) Bit [4:0] Hash result 1 destination port number (Default 01) 14.6.6 TRUNK0_HASH2 – Trunk group 0 hash result 2 destination ...
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TRUNK1_HASH0 – Trunk group 1 hash result 0 destination port number CPU Address:h20C Accessed by CPU, serial interface (R/W) Bit [4:0] Hash result 0 destination port number (Default 04) 14.6.12 TRUNK1_HASH1 – Trunk group 1 hash result 1 destination ...
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TRUNK2_HASH0 – Trunk group 2 hash result 0 destination port number CPU Address:h211 Accessed by CPU, serial interface (R/W) Bit [4:0] Hash result 0 destination port number (Default 0x19) 0x19 = Gigabit port 1 0x1A = Gigabit port 2 ...
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Multicast_HASH0-1 – Multicast hash result 0 mask byte 1 CPU Address:h221 Accessed by CPU, serial interface (R/W) Bit [7:0] (Default FF) 14.6.18.3 Multicast_HASH0-3 – Multicast hash result 0 mask byte 3 CPU Address:h223 Accessed by CPU, serial interface (R/W) ...
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Multicast_HASH2-3 – Multicast hash result 2 mask byte 3 CPU Address:h22B Accessed by CPU, serial interface (R/W) Bit [7:0] (Default FF) 14.6.18.10 Multicast_HASH3-0 – Multicast hash result 3 mask byte 0 CPU Address:h22C Accessed by CPU, serial interface (R/W) ...
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MAC2 – CPU Mac address byte 2 CPU Address:h302 Accessed by CPU Bit [7:0] Byte 2 of the CPU MAC address. (Default 00) 14.7.4 MAC3 – CPU Mac address byte 3 CPU Address:h303 Accessed by CPU Bit [7:0] Byte ...
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INTP_MASK0 – Interrupt Mask for MAC Port 0,1 CPU Address:h310 Accessed by CPU, serial interface (R/W) The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted ( Default 0xFF ...
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INTP_MASK7 – Interrupt Mask for MAC Port 14,15 CPU Address:h317 Accessed by CPU, serial interface (R/W) 14.7.16 INTP_MASK12 – Interrupt Mask for MAC Port G1,G2 CPU Address:h31C Accessed by CPU, serial interface (R/W) 14.7.17 RQS – Receive Queue Select ...
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CPU receive queue status - Bit [3:0]: Queue not empty - Bit [4]: Head of line entry for Queue 0 is valid for too long. CPU Queue 0 has no WRED threshold. - Bit [7:5]: Head of ...
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SCAN Control Register (default 00) CPU Address h404 Accessed by CPU (R/ Ratio SCAN is used when fast learning is enabled (SE_OPMODE bit 0 used for setting up the report rate for ...
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Bit [4]: • Per VLAN Multicast Flow Control (Default – Disable - 1 – Enable Bit [5]: • Select processor multicast queue size - entries - entries Bit [6]: • Select ...
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AVPML – VLAN Tag Priority Map Address h0AD; CPU Address:h503 Accessed by CPU, serial interface and VP2 Registers AVPML, AVPMM, and AVPMH allow the eight VLAN Tag priorities to map into eight ...
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Map VLAN priority into eight level transmit priorities: Bit [1:0]: Priority when the VLAN tag priority field is 5 (Default 0) Bit [4:2]: Priority when the VLAN tag priority field is 6 (Default 0) Bit [7:5]: Priority when the VLAN ...
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Map TOS field in IP packet into eight level transmit priorities: Bit [1:0]: Priority when the TOS field is 5 (Default 0) Bit [4:2]: Priority when the TOS field is 6 (Default 0) Bit [7:5]: Priority when the TOS field ...
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Bit [5]: Frame drop priority when TOS field is 5 (Default 0) Bit [6]: Frame drop priority when TOS field is 6 (Default 0) Bit [7]: Frame drop priority when TOS field is 7 (Default 0) 14.9.12 BMRC - Broadcast/Multicast ...
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Bit [4:0]: In multiples of two frames (granularity). Used for triggering MC flow control when destination port’s multicast best effort queue reaches MCC threshold.(Default 0x10) Bit [7:5]: Flow control reaction period (Default 2) Granularity 4 uSec. 14.9.15 PR100 – Port ...
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SFCB – Share FCB Size Address h0BA), CPU Address 510 Accessed by CPU, serial interface and I 7 Shared pool buffer size Bits [7:0]: Expressed in multiples of 4 packets. Buffer reservation for shared pool. • ...
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C5RS – Class 5 Reserve Size Address h0BE; CPU Address 514 Accessed by CPU, serial interface and I 7 Class 5 FCB Reservation Buffer reservation for class 5. Granularity 1. (Default 0) 14.9.22 C6RS – Class ...
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Classes Byte Limit Set 1 Accessed by CPU, serial interface and I 2 • QOSC03 – BYTE_C11 (I C Address h0C4, CPU Address 51a) 2 • QOSC04 – BYTE_C12 (I C Address h0C5, CPU Address ...
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Granularity when Delay bound is used: QOSC17 and QOSC16: 256 bytes, QOSC15 and QOSC14: 512 bytes, QOSC13 and QOSC12: 1024 bytes. Granularity when WFQ is used: QOSC17 to QOSC12: 1024 bytes 14.9.29 Classes Byte Limit Giga Port 2 Accessed by ...
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QOSC28[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4. QOSC29[7]: Priority service allow flow control for the ports select this parameter set. QOSC29[6]: Flow control pause best effort traffic only 14.9.32 Classes WFQ ...
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W5 - QOSC45[5:0] – CREDIT_C5_G1 (CPU Address 544) • QOSC46[5:0] – CREDIT_C6_G1 (CPU Address 545) • QOSC47[5:0] – CREDIT_C7_G1 (CPU Address 546) QOSC40 through QOSC47 represents the set of WFQ parameters for Gigabit port 24. ...
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RDRC0 – WRED Rate Control Address 0FB, CPU Address 553 Accessed by CPU, Serial Interface and Rate Bits [7:4]: Corresponds to the frame drop percentage X% for WRED. Granularity 6.25%. Bits[3:0]: ...
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User_Port [7:0] priority register. The port priority can be individually enabled/disabled via User_Port_Enable register. The User Defined Range provides a range of logical port numbers with the same priority level. Programming is similar to the User Defined ...
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USER_PORT_[3:2]_PRIORITY - Address h0E7, CPU Address 591 Accessed by CPU, serial interface and Priority 3 Drop 14.9.40.4 USER_PORT_[5:4]_PRIORITY - Address h0E8, CPU Address 592 Accessed by CPU, ...
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Priority 1 - Well Known port 512 for TCP/UDP. (Default 00) 14.9.40.8 WELL_KNOWN_PORT[3:2] PRIORITY Address h0EC, CPU Address 596 Accessed by CPU, serial interface and Priority 3 Drop Priority 2 - Well ...
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WELL KNOWN_PORT_ENABLE [7:0] – Address h0EF, CPU Address 599 Accessed by CPU, serial interface and 1– Enable - 0 - Disable (Default 00) 14.9.40.12 RLOWL ...
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RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bit [3:1] Transmit Priority Bits [0]: Drop Priority 14.9.41 CPUQOSC123 CPU Address: 5a0, 5a1, 5a2 Accessed by CPU and serial interface (R/W) C ...
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MII_OP1 – MII Register Option Address F1, CPU Address:h601 Accessed by CPU, serial interface and Speed bit location Bits [3:0]: Duplex bit location in vendor specified register Bits [7:4]: Speed bit location ...
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Bit [4]: Disable IP Multicast Suppor t (Default 1) • 0 – Enable IP Multicast Support • 1 – Disable IP Multicast Support When enable, IGMP packets are identified by search engine and are passed to the CPU for processing. ...
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MIIC3 – MII Command Register 3 CPU Address:h606 Accessed by CPU and serial interface only (R/ Rdy Valid • Bits [4:0] - PHY_AD – 5 Bit PHY Address • Bit [6] - VALID – Data Valid ...
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DEVICE Mode CPU Address:h60a Accessed by CPU and serial interface (R/W) Bit [1:0]:Reserved. Must be set to ‘0’ (Default 0) Bit [2]: Support <= 1536 frames 0: <= 1518 bytes (<= 1522 bytes with VLAN tag) (Default) 1: <= ...
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MIRROR1_DEST – Port Mirror destination CPU Address 701 Accessed by CPU, serial interface (R/W) (Default 17 Dest Port Select • Bit [4:0]: Port Mirror Destination When port mirroring is enable, destination port can not serve as ...
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Group F Address) CPU Access Group 14.12.1 GCR-Global Control Register CPU Address: hF00 Accessed by CPU and serial interface. (R/ Bit [0]: Store configuration (Default = 0) Write ‘1’ followed by ‘0’ to store configuration into external ...
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Bit [7:6]: Revision 00: Initial Silicon 01: XA1 Silicon 10: Production Silicon 14.12.2.1 DCR1-Giga port status CPU Address: hF02 Accessed by CPU and serial interface. (RO CIC Bit [1:0]: Giga port 0 strap option Giga port 1 strap ...
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DPST – Device Port Status Register CPU Address:hF03 Accessed by CPU and serial interface (R/W) Bit[4:0]: Read back index register. This is used for selecting what to read back from DTST. (Default 00) 14.12.4 DTST – Data read back ...
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When bit is 1: Bit [0] – Flow control enable Bit [1] – Full duplex port Bit [2] – Fast Ethernet port (if not gigabit port) Bit [3] – Link is down Bit [4] – Giga port Bit [5] – ...
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OECLK - Internal OE_CLK delay from SCLK CPU Address: hF07 Accessed by serial interface (RW) The OE_CLK is used for generating the OE0 and OE1 signals. PD[15:13] OECLK Delay 000b 80h 8 Buffers Delay 001b 40h 7 Buffers Delay ...
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Bit [9] Restart Auto Negotiation Restart auto-negotiation process Normal operation (Default). Bit [8:7] Reserved. Bit [6] Speed Selection Bit [6][13 Reserved 1000 Mb/s (Default =100 Mb ...
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Advertisement Register MII Address: h04 Read/Write Bit [15] Next Page 1 = Has next page capabilities not has next page capabilities (Default). Bit [14] Reserved. Always read back as “0”. Read Only. Bit [13:12] Remote Fault. ...
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Expansion Register MII Address: h06 Read Only Bit [15:2] Reserved. Always read back as “0”. Bit [1] Page Received new page has been received new page has not been received. Bit [0] Reserved. ...
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BGA and Ball Signal Descriptions 15.1 BGA Views (TOP Views) 15.1.1 Encapsulated view in unmanaged mode ...
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Encapsulated view in managed mode LA_D LA_D LA_D LA_D LA_D LA_A LA_D LA_D LA_D LA_D LA_D LA_D LA_A ...
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Ball – Signal Descriptions in Managed Mode All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive. 15.2.1 Ball Signal Descriptions in Managed Mode Ball No(s) CPU BUS Interface ...
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Ball No(s) E12 LA_WE1# C8 LA_OE# A9 LA_OE0# B9 LA_OE1# F4, F5, G4, G5, H4, H5, J4, LB_D[63:0] J5, K4, K5, L4, L5, M4, M5, N4, N5, G3, H1, H2, H3, J1, J2, J3, K1, K2, K3, L1, L2, L3, ...
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Ball No(s) Fast Ethernet Access Ports [15:0] RMII R28 M_MDC P28 M_MDIO R29 M_CLKI AF21, AJ19, AF18, AJ17, M[15:0]_RXD[1] AJ15, AF15, AJ13, AF12, AJ11, AJ9, AF9, AJ7, AF6, AJ5, AJ3, AF1 AE21, AH19, AH20, AH17, M[15:0]_RXD[0] AH15, AE15, AH13, AE12, ...
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Ball No(s) W27, Y29, Y28, Y25, AA29, M25_RXD[9:0] AA28, AA27, AB29, AB28, AB27 T26 M25_TX_EN R26 M25_TX_ER T27 M25_ MTXCLK T25 M25_ TXCLK P29 GREF_CLK0 K25, K26, M25, L26, M26, M26_TXD[9:0] L25, N26, N25, P26, P25 F28 M26_RX_DV G28 M26_RX_ER ...
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Ball No(s) E28 G2_RXTX#/TS TOUT6 A27 G2_DPCOL#/T STOUT7 B27 G2_LINK#/TST OUT8 C27 INIT_DONE/TS TOUT9 D27 INIT_START/TS TOUT10 C26 CHECKSUM_O K/TSTOUT11 D26 FCB_ERR/TST OUT12 D25 MCT_ERR/TST OUT13 D24 BIST_IN_PRC/ TSTOUT14 E24 BIST_DONE/TS TOUT15 Test Facility U3, C10 T_MODE0, T_MODE1 Ball No(s) ...
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Ball No(s) System Clock, Power, and Ground Pins E1 SCLK K12, K13, K17,K18 M10, VDD N10, M20, N20, U10, V10, U20, V20, Y12, Y13, Y17, Y18 F13, F14, F15, F16, F17, VCC N6, P6, R6, T6, U6, N24, P24, R24, ...
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Ball No(s) AC29, AE28, AJ27, RESERVED AF27, AJ25, AF24, AH23, AE19, AC27, AF29, AG27, AF26, AG25, AG23, AF23, AG21, AC28, AF28, AH27, AE27, AH25, AE24, AF22, AF20, AD29, AG28, AJ26, AE26, AJ24, AE23, AJ22, AJ20, AD27, AH28, AG26, AE25, AG24, ...
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Ball No(s) A27 TSTOUT7 B27 TSTOUT8 C27 TSTOUT9 D27 TSTOUT10 C26 TSTOUT11 D26 TSTOUT12 D25 TSTOUT13 D24 TSTOUT14 E24 TSTOUT15 T26, R26 G0_TXEN, G0_TXER ZL50418 Symbol I/O Default 1 Default 1 Default 1 Default 1 Default 1 Default 1 Default ...
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Ball No(s) F26, E26 G1_TXEN, G1_TXER AE20, AJ18, AJ21, M[15:0] TXEN AJ16, AJ14, AE14, AJ12, AE11, AJ10, AJ8, AE8, AJ6, AE5, AJ4, AG1, AE1 C21 P_D[9] C19, B19, A19 P_D[15:13] C20, B20, A20 P_D[12:10] Notes: # =Active low signal Input ...
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Ball – Signal Descriptions in Unmanaged Mode Ball No(s) Symbol Interface Note: In unmanaged mode, Use I A24 SCL A25 SDA Serial Control Interface A26 STROBE B26 D0 C25 AUTOFD Frame Buffer Interface D20, B21, D19, ...
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Ball No(s) Symbol A9 LA_OE0# B9 LA_OE1# F4, F5, G4, G5, H4, LB_D[63:0] H5, J4, J5, K4, K5, L4, L5, M4, M5, N4, N5, G3, H1, H2, H3, J1, J2, J3, K1, K2, K3, L1, L2, L3, M1, M2, M3, ...
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Ball No(s) Symbol R29 M_CLKI AF21, AJ19, AF18, M[15:0]_RXD[1] AJ17, AJ15, AF15, AJ13, AF12, AJ11, AJ9, AF9, AJ7, AF6, AJ5, AJ3, AF1 AE21, AH19, AH20, M[15:0]_RXD[0] AH17, AH15, AE15, AH13, AE12, AH11, AH9, AE9, AH7, AE6, AH5, AH2, AF2 AH21, ...
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Ball No(s) Symbol P29 GREF_CLK0 K25, K26, M25, L26, M26_TXD[9:0] M26, L25, N26, N25, P26, P25 F28 M26_RX_DV G28 M26_RX_ER E25 M26_CRS G29 M26_COL F29 M26_RXCLK J27, K29, K29, K28, M26_RXD[9:0] K27, L29, L28, L27, M29, M28, M27 F26 M26_TX_EN ...
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Ball No(s) Symbol D26 FCB_ERR/TSTOUT 12 D25 MCT_ERR/TSTOUT 13 D24 BIST_IN_PRC/TST OUT14 E24 BIST_DONE/TSTO UT15 Trunk Enable C22 TRUNK0 A21 TRUNK1 B24 TRUNK2 Test Facility U3, C10 T_MODE0, T_MODE1 F3 SCAN_EN E27 SCANMODE System Clock, Power, and Ground Pins E1 ...
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Ball No(s) Symbol M12, M13, M14, M15, VSS M16, M17, M18, N12, N13, N14, N15, N16, N17, N18, P12, P13, P14, P15, P16, P17, P18, R12, R13, R14, R15, R16, R17, R18, T12, T13, T14, T15, T16, T17, T18, U12, ...
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Ball No(s) Symbol C29 TSTOUT0 D29 TSTOUT1 E29 TSTOUT2 B28 TSTOUT3 C28 TSTOUT4 D28 TSTOUT5 E28 TSTOUT6 A27 TSTOUT7 B27 TSTOUT8 C27 TSTOUT9 D27 TSTOUT10 C26 TSTOUT11 D26 TSTOUT12 D25 TSTOUT13 D24 TSTOUT14 ZL50418 I/O Default 1 GIGA Link polarity ...
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Ball No(s) Symbol E24 TSTOUT15 T26, R26 G0_TXEN, G0_TXER F26, E26 G1_TXEN, G1_TXER AE20, AJ18, AJ21, M[15:0]_TXEN AJ16, AJ14, AE14, AJ12, AE11, AJ10, AJ8, AE8, AJ6, AE5, AJ4, AG1, AE1, C21 P_D C19, B19, A19 OE_CLK[2:0] C20, B20, A20 LA_CLK[2:0] ...
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Ball – Signal Name in Unmanaged Mode Ball No. Signal Name D20 LA_D[63] B21 LA_D[62] D19 LA_D[61] E19 LA_D[60] D18 LA_D[59] E18 LA_D[58] D17 LA_D[57] E17 LA_D[56] D16 LA_D[55] E16 LA_D[54] D15 LA_D[53] E15 LA_D[52] D14 LA_D[51] E14 LA_D[50] ...
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Ball No. Signal Name D9 LA_D[31] E9 LA_D[30] D8 LA_D[29] E8 LA_D[28] D7 LA_D[27] E7 LA_D[26] D6 LA_D[25] E6 LA_D[24] D5 LA_D[23] E5 LA_D[22] D4 LA_D[21] E4 LA_D[20] AB4 LB_D[21] AB5 LB_D[20] AC4 LB_D[19] AC5 LB_D[18] AD4 LB_D[17] AD5 LB_D[16] ...
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Ball No. Signal Name AD3 LB_D[0] N3 LB_A[20] N2 LB_A[19] N1 LB_A[18] P3 LB_A[17] P2 LB_A[16] P1 LB_A[15] R5 LB_A[14] R4 LB_A[13] R3 LB_A[12] R2 LB_A[11] R1 LB_A[10] T5 LB_A[9] T4 LB_A[8] T3 LB_A[7] T2 LB_A[6] T1 LB_A[5] W3 LB_A[4] ...
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Ball No. Signal Name AH28 RESERVED AG26 RESERVED AE25 RESERVED AG24 RESERVED AE22 RESERVED AJ23 RESERVED AG20 RESERVED AE18 M[15]_TXD[1] AG18 M[14]_TXD[1] AE16 M[13]_TXD[1] AG16 M[12]_TXD[1] AG14 M[11]_TXD[1] AE13 M[10]_TXD[1] AG12 M[9]_TXD[1] AE10 M[8]_TXD[1] AG10 M[7]_TXD[1] AG8 M[6]_TXD[1] AE7 M[5]_TXD[1] ...
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Ball No. Signal Name AF16 M[13]_TXD[0] AH16 M[12]_TXD[0] AH14 M[11]_TXD[0] AF13 M[10]_TXD[0] AH12 M[9]_TXD[0] AF10 M[8]_TXD[0] AH10 M[7]_TXD[0] B27 G2_LINK#/TSTOUT[8] A27 G2_DPCOL#/TSTOUT[7 ] E28 G2_RXTX#/TSTOUT[6] D28 G1_LINK#/TSTOUT[5] C28 G1_DPCOL#/TSTOUT[4 ] B28 G1_RXTX#/TSTOUT[3] E29 LED_BIT/TSTOUT[2] D29 LED_SYN/TSTOUT[1] C29 LED_CLK/TSTOUT[0] N29 GREF_CLK1 ...
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Ball No. Signal Name D1 AGND D22 SCANCOL E23 SCANLINK E27 SCANMODE N28 N27 F2 RESIN# G2 RESETOUT# B22 Reserved A22 Reserved C23 Reserved B23 Reserved A23 Reserved C24 Reserved D23 SCANCLK T27 M25_MTXCLK F27 M26_MTXCLK C20 LA_CLK2 B20 LA_CLK1 ...
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Ball – Signal Name in Managed Mode Ball Signal Name No. D20 LA_D[63] B21 LA_D[62] D19 LA_D[61] E19 LA_D[60] D18 LA_D[59] E18 LA_D[58] D17 LA_D[57] E17 LA_D[56] D16 LA_D[55] E16 LA_D[54] D15 LA_D[53] E15 LA_D[52] D14 LA_D[51] E14 LA_D[50] ...
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Ball Signal Name No. B14 LA_D[32] D9 LA_D[31] E9 LA_D[30] D8 LA_D[29] E8 LA_D[28] D7 LA_D[27] E7 LA_D[26] D6 LA_D[25] E6 LA_D[24] D5 LA_D[23] E5 LA_D[22] D4 LA_D[21] E4 LA_D[20] AB4 LB_D[21] AB5 LB_D[20] AC4 LB_D[19] AC5 LB_D[18] AD4 LB_D[17] ...
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Ball Signal Name No. AD1 LB_D[2] AD2 LB_D[1] AD3 LB_D[0] N3 LB_A[20] N2 LB_A[19] N1 LB_A[18] P3 LB_A[17] P2 LB_A[16] P1 LB_A[15] R5 LB_A[14] R4 LB_A[13] R3 LB_A[12] R2 LB_A[11] R1 LB_A[10] T5 LB_A[9] T4 LB_A[8] T3 LB_A[7] T2 LB_A[6] ...
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Ball Signal Name No. AG1 M[1]_TXEN AE1 M[0]_TXEN AD27 RESERVED AH28 RESERVED AG26 RESERVED AE25 RESERVED AG24 RESERVED AE22 RESERVED AJ23 RESERVED AG20 RESERVED AE18 M[15]_TXD[1] AG18 M[14]_TXD[1] AE16 M[13]_TXD[1] AG16 M[12]_TXD[1] AG14 M[11]_TXD[1] AE13 M[10]_TXD[1] AG12 M[9]_TXD[1] AE10 M[8]_TXD[1] ...
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Ball Signal Name No. AH22 RESERVED AE17 RESERVED AG19 M[15]_TXD[0] AH18 M[14]_TXD[0] AF16 M[13]_TXD[0] AH16 M[12]_TXD[0] AH14 M[11]_TXD[0] AF13 M[10]_TXD[0] AH12 M[9]_TXD[0] AF10 M[8]_TXD[0] AH10 M[7]_TXD[0] B27 G2_LINK#/TSTOUT[8] A27 G2_DPCOL#/TSTOUT [7] E28 G2_RXTX#/TSTOUT[6 ] D28 G1_LINK#/TSTOUT[5] C28 G1_DPCOL#/TSTOUT [4] B28 ...
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Ball Signal Name No. A26 P_WE B26 P_RD C25 P_CS A24 P_A1 A25 P_A0 F1 AVCC D1 AGND D22 SCANCOL E23 SCANLINK E27 SCANMODE N28 N27 F2 RESIN# G2 RESETOUT# B22 P_DATA5 A22 P_DATA4 C23 P_DATA3 B23 P_DATA2 A23 P_DATA1 ...
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AC/DC Timing 15.5.1 Absolute Maximum Ratings Storage Temperature Operating Temperature Maximum Junction Temperature Supply Voltage VCC with Respect to V Supply Voltage VDD with Respect to V Voltage on Input Pins Caution: Stress above those listed may damage the ...
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Symbol Parameter Description θ Thermal resistance between junction and board jb 15.5.4 Typical Reset & Bootstrap Timing Diagram RESIN# RESETOUT# R1 Bootstrap Pins Outputs Figure 18 - Typical Reset & Bootstrap Timing Diagram Symbol Parameter R1 Delay until RESETOUT# is ...
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Typical CPU Timing Diagram for a CPU Write Cycle P_ADDR P_CS# T P_WE# DATA to ZL5041x DATA to VTX2600 Set up time Figure 19 - Typical CPU Timing Diagram for a CPU Write Cycle Description Write Cycle Write Set ...
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Typical CPU Timing Diagram for a CPU Read Cycle P_ADDR P_CS# T P_RD# DATA to CPU Valid time Figure 20 - Typical CPU Timing Diagram for a CPU Read Cycle Description Read Cycle Read Set up Time Read Active ...
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Local Frame Buffer SBRAM Memory Interface 15.6.1 Local SBRAM Memory Interface Figure 21 - Local Memory Interface – Input Setup and Hold Timing LA_OE[1:0]# Figure 22 - Local Memory Interface - Output Valid Delay Timing ZL50418 LA_CLK L1 L2 ...
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Symbol L1 LA_D[63:0] input set-up time L2 LA_D[63:0] input hold time L3 LA_D[63:0] output valid delay L4 LA_A[20:3] output valid delay L6 LA_ADSC# output valid delay L7 LA_WE[1:0]#output valid delay L8 LA_OE[1:0]# output valid delay L9 LA_WE# output valid delay ...
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LB_CLK LB_D[31:0] LB_A[21:2] LB_ADSC# LB_WE[1:0]# LB_OE[1:0]# LB_WE# LB_OE# Figure 24 - Local Memory Interface - Output Valid Delay Timing Symbol Parameter L1 LB_D[63:0] input set-up time L2 LB_D[63:0] input hold time L3 LB_D[63:0] output valid delay L4 LB_A[20:3] output valid ...
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AC Characteristics 15.8.1 Reduced Media Independent Interface M[23:0] _TXD[1:0] 15 Figure Characteristics – Reduced Media Independent Interface M[23:0]_CRS_DV 15 Figure Characteristics – Reduced Media Independent Interface Symbol M2 M[15:0]_RXD[1:0] Input Setup Time M3 ...
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Gigabit Media Independent Interface - Port A M25_TXD [7:0] M25_RXD[7:0] M25_RX_CRS Figure Characteristics – Gigabit Media Independent Interface Symbol Parameter G1 M[25]_RXD[7:0] Input Setup Times G2 M[25]_RXD[7:0] Input Hold Times G3 M[25]_RX_DV Input Setup Times G4 ...
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Ten Bit Interface - Port A M25_TXD [9:0] Figure 29 - Gigabit TBI Interface Transmit Timing M25_RXCLK M25_COL M25_RXD[9:0] Figure 30 - Gigabit TBI Interface Receive Timing Symbol Parameter T1 M25_TXD[9:0] Output Delay Time Symbol Parameter T2 M25_RXD[9:0] Input ...
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Gigabit Media Independent Interface - Port B M26_TXD [7:0] M26_RXD[7:0] M26_RX_CRS Figure Characteristics – Gigabit Media Independent Interface Symbol Parameter G1 M[26]_RXD[7:0] Input Setup Times G2 M[26]_RXD[7:0] Input Hold Times G3 M[26]_RX_DV Input Setup Times G4 ...
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Symbol Parameter G13 M[26]_TX_EN Output Delay Times G14 M[26]_TX_ER Output Delay Times Table Characteristics – Gigabit Media Independent Interface (continued) 15.8.5 Ten Bit Interface - Port B M26_TXCLK M26_TXD [9:0] Figure 33 - Gigabit TBI Interface Transmit ...
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LED Interface Figure Characteristics – LED Interface Symbol Parameter LE5 LED_SYN Output Valid Delay LE6 LED_BIT Output Valid Delay Table Characteristics – LED Interface 15.8.7 SCANLINK SCANCOL Output Delay Timing SCANCLK SCANLINK SCANCOL ...
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Symbol C1 SCANLINK input set-up time C2 SCANLINK input hold time C3 SCANCOL input setup time C4 SCANCOL input hold time C5 SCANLINK output valid delay C7 SCANCOL output valid delay Table 29 - SCANLINK, SCANCOL Timing 15.8.8 MDIO Input ...
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Symbol D1 MDIO input setup time D2 MDIO input hold time D3 MDIO output delay time 2 15.8 Input Setup Timing Symbol S1 SDA input setup time S2 SDA input hold time S3* SDA output delay time * ...
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Serial Interface Setup Timing STROBE D0 STROBE AutoFd Figure 43 - Serial Interface Output Delay Timing Symbol D1 D0 setup time D2 D0 hold time D3 AutoFd output delay time D4 Strobe low time D5 Strobe high time ZL50418 ...
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NOTE: 1. CONTROLLING DIMENSIONS ARE DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS THE NUMBER OF ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...