HC230 ALTERA [Altera Corporation], HC230 Datasheet
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HC230 Summary of contents
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This section provides designers with the data sheet specifications HardCopy internal architecture, configuration and JTAG boundary-scan testing information, DC operationg conditions, AC timing parameters, a reference to power consumption, and ordering information for HardCopy II devices. This section contains the ...
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Revision History Section I–2 Preliminary HardCopy Series Handbook, Volume 1 Altera Corporation ...
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... HardCopy II companion device. HardCopy II devices are also supported through other front-end design tools from Synopsys, Synplicity, and Mentor Graphics Feature HardCopy II structured ASICs are manufactured all-layer-copper metal fabrication process (up to nine layers of metal). Overview HardCopy II devices offer the following features: ■ ...
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HardCopy Series Handbook, Volume 1 ■ ■ 1 ■ ■ ■ ■ 1–2 Preliminary System performance up to 350 MHz Up to 50% power reduction (dynamic and static) for typical designs compared to Stratix II FPGA prototypes The actual performance ...
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... September 2008 HC210W (1) HC210 HC220 1,000,000 1,000,000 1,900,000 190 190 0 0 875,520 875,520 3,059,712 308 334 Feature Overview Table 1–1 HC230 HC240 2,900,000 3,600,000 408 614 768 ( 6,368,256 8,847,360 494 698 951 Preliminary 1–3 ...
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... Package Device HC210W 484-pin FineLine BGA HC210 484-pin FineLine BGA HC220 672-pin FineLine BGA HC220 780-pin FineLine BGA HC230 1,020-pin FineLine BGA HC240 1,020-pin FineLine BGA HC240 1,508-pin FineLine BGA Notes to Table 1–2: (1) The HC210W device uses a wire bond package while the Stratix II FPGA prototype device uses a pin-compatible flip-chip package ...
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... Length × width 23 × 23 (mm × mm) Device HC210W 308 HC210 HC220 HC230 HC240 Notes to Table 1–3: (1) The Quartus II I/O pin counts include an additional pin (PLLENA) which is not available as a general-purpose I/O pin. The PLLENA pin can only be used to enable the PLLs. The I/O pin counts include the dedicated CLK input pins, which can be used for clock signals or data inputs. ...
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HardCopy Series Handbook, Volume 1 Table 1–4. Document Revision History (Part Date and Document Version December 2006 ● Minor updates for the Quartus II software version 6.1.0 v2.4 ● Merged Table 1-3 and Table 1-4 ● Added ...
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... FineLine BGA FineLine BGA (334) (492) 780-pin FineLine BGA (494) and Features Table 2–1 provides HC230 HC240 2,900,000 3,600,000 (3) 614 768 6 9 6,368,256 8,847,360 1,020-pin 1,020-pin FineLine BGA FineLine BGA (698) (742) ...
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... A fine-grain architecture consisting of an array of HCells extends the die reduction and cost 2–2 Preliminary (1) HC210 HC220 EP2S30 EP2S60 EP2S60 EP2S90 EP2S90 EP2S130 HC230 HC240 EP2S90 EP2S180 EP2S130 EP2S180 Altera Corporation September 2008 ...
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... V) as Stratix II FPGAs. Additionally, almost all architectural features in HardCopy II devices are functionally equivalent to features found in the Stratix II FPGA architecture. HardCopy II devices feature HCells, memory blocks, PLLs, and IOEs Figure 2–1. Example Block Diagram of HC230 Device M4K RAM Blocks IOE Array of HCells ...
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... Logic blocks, known as HCells, are the basic building block of the core logic in HardCopy II devices and replace Stratix II adaptive logic modules (ALMs). HCells implement logic and DSP functions. ...
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Altera Corporation September 2008 HardCopy II and Stratix II Similarities and Differences Unlike Stratix II FPGAs, the HardCopy II M4K block contents cannot be pre-loaded with a Memory Initialization File ...
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HardCopy Series Handbook, Volume 1 HCells HardCopy II devices are built using an array of fine-grained architecture blocks called HCells. HCells are a collection of logic transistors based on 1 process technology, similar to Stratix II devices. ...
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Only HCells that are required to implement the design’s DSP functions are enabled. HCells not needed for DSP functions can be used for ALM configurations, which results in efficient logic usage. In addition to area management, the placement of these ...
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... HardCopy II M4K memory blocks, the 2–8 Preliminary Up to four 18-bit independent multipliers Up to two 8-bit multiplier-accumulators One 36-bit multiplier HC210 HC220 190 190 408 0 0 875,520 3,059,712 (Table HC230 HC240 614 768 6,368,256 8,847,360 Altera Corporation September 2008 2–3). ...
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The designer needs to take these into consideration when designing logic that might evaluate the initial power-up values of the memory block. HardCopy II embedded memory consists of M4K and M-RAM memory blocks and ...
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HardCopy Series Handbook, Volume 1 Table 2–4. HardCopy II Embedded Memory Features Feature Maximum performance (1), (4) Total RAM bits (including parity bits) Configurations Parity bits Byte enable Pack mode Address clock enable Single-port memory Simple dual-port memory True dual-port ...
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... PLLs are available in each device density. shows the location of each PLL. During the prototyping stage Note (1) Fast PLLs PLLs and Clock Networks Notes (1), (2), (3) M-RAM Blocks (Table 2–5). HC220 HC230 HC240 Table 2–6 Enhanced PLLs ...
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... HardCopy Series Handbook, Volume 1 Table 2–6. HardCopy II PLLs Available (Part Device HC220 v v HC230 HC240 Note to Table 2–6: (1) PLL performance in the HC210W device may differ from the Stratix II FPGA prototype. Figure 2–3. HardCopy II PLL Locations 1 CLK[3..0] 2 PLLs ...
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PLL functionality in HardCopy II devices remains the same as in Stratix II FPGA PLLs. Therefore, the HardCopy II PLLs support PLL reconfiguration (the PLL can be dynamically configured in user mode). HardCopy II enhanced and fast PLLs support a ...
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HardCopy Series Handbook, Volume 1 Clock Networks There are 16 clock pins (CLK[15..0]) in HardCopy II devices that can drive either the global- or regional-clock networks. The CLK pins can drive clock ports or data inputs. HardCopy II devices provide ...
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The IOE feature set in HardCopy II devices can be classified in one of three categories: ■ ■ ■ All I/O pins in Stratix II FPGAs support general-purpose I/O standards, which includes the LVTTL and LVCMOS I/O standards. In Stratix ...
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HardCopy Series Handbook, Volume 1 Table 2–9. HardCopy II Supported I/O Standards (Part I/O Standard Type SSTL-2 class II Voltage referenced SSTL-18 class I Voltage referenced SSTL-18 class II Voltage referenced 1.8-V HSTL class I Voltage referenced ...
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Table 2–9. HardCopy II Supported I/O Standards (Part I/O Standard Type LVPECL Differential Notes to Table 2–9: (1) Pseudo-differential HSTL and SSTL inputs only use the positive-polarity input in the speed path. The negative input is not ...
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HardCopy Series Handbook, Volume 1 Figure 2–4. I/O Type Support in HC210 and HC220 Devices Memory Interface IOEs Bank 2 High-Speed IOEs I/O Banks 1 & 2 Support 3.3-, PLL 1 2.5- & 1.8-V LVTTL/LVCMOS, 1.5-V PLL 2 LVCMOS, LVDS ...
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... Figure 2–5. I/O Type Support in HC230 Devices PLL 7 Memory Interface IOEs Bank 2 High-Speed IOEs I/O Banks 1 & 2 Support 3.3-, PLL 1 2.5- & 1.8-V LVTTL/LVCMOS, 1.5-V PLL 2 LVCMOS, LVDS & HyperTransport Technology Bank 1 High-Speed IOEs Bank 8 PLL 8 Memory Interface IOEs Altera Corporation September 2008 Notes (1), (2) Bank 11 Bank 9 ...
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... The general purpose IOEs in HC210 and HC220 devices are located on the right side and at the bottom of the device. The general purpose IOEs in HC230 devices are located on the right side of the device. (Directions are based on a top view of the silicon die.) HC240 devices do not have general purpose IOEs ...
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IOEs except for the PCI clamping diode. In Stratix II FPGAs, all IOEs support the general purpose IOE features except the PCI diode, which is only supported on the top and bottom ...
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... Memory Interface IOE Memory interface IOEs in HC210 and HC220 devices are located on the top of the device. Memory interface IOEs in HC230 and HC240 devices are located on the top and the bottom of the device. In Stratix II FPGAs, the top and bottom IOEs support the memory interface IOE features. ...
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... Package HC210W 484-pin FineLine BGA (Wire Bond) HC210 484-pin FineLine BGA HC220 672-pin FineLine BGA 780-pin FineLine BGA HC230 1,020-pin FineLine BGA Altera Corporation September 2008 SSTL-2 class I and II SSTL-18 class I and II 1.8-V HSTL class I and II 1.5-V HSTL class I and II LVTTL/LVCMOS SSTL-2 class I and II SSTL-18 class I and II 1 ...
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HardCopy Series Handbook, Volume 1 Table 2–11. DQS and DQ Bus Mode Support (Part Device Package HC240 1,020-pin FineLine BGA 1,508-pin FineLine BGA The programmable drive strengths available vary depending on the I/O standard used. The options ...
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... High-Speed IOE High-speed IOEs in HC210, HC220, and HC230 devices are located on the left side of the device. High-speed IOEs in HC240 devices are located on the left and right sides of the device. (Directions are based on a top view of the silicon die.) Unlike Stratix II left and right side I/O pins, HardCopy II left and right side I/O pins do not support SSTL or HSTL I/O standards or the PCI clamping diode ...
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... High-speed IOEs support non-calibrated on-chip series termination and differential termination on the receiver channels. 50- and 25-Ω on-chip series termination is available for 3.3- or 2.5-V I/O standards. 50-Ω on-chip series termination is available for 1.8- and 1.5-V I/O standards (pending characterization). 2–26 Preliminary HC220 HC230 672-Pin 780-Pin 1,020-Pin FineLine FineLine FineLine BGA ...
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... Modes structured ASICs follow the same principle, enabling traditional ASIC-like power up. Although prototyping FPGAs require configuration upon power up, the HardCopy II structured ASICs do not need to be configured. HardCopy II devices do not support configuration and designers should take this into account in the prototyping-to-production development process ...
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HardCopy Series Handbook, Volume 1 Document Table 2–15 Revision History Table 2–15.Document Revision History Date and Document Version September 2008, Updated chapter number and metadata. v2.5 June 2007, v2.4 ● Added Note 4 to December 2006 ● Updated Table 2–1, ...
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... HardCopy II devices support the JTAG instructions shown in Table 3–1. HardCopy II JTAG Instructions (Part JTAG Instruction SAMPLE/PRELOAD EXTEST BYPASS Altera Corporation September 2008 3. Boundary-Scan Support ® II structured ASICs provide Joint Test Action Group Instruction Code 00 0000 0101 00 0000 1111 (1) 11 1111 1111 . CCIO Table 3–1. ...
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HardCopy Series Handbook, Volume 1 Table 3–1. HardCopy II JTAG Instructions (Part JTAG Instruction USERCODE IDCODE HIGHZ CLAMP Note to (1) f The BSDL files for HardCopy II devices are different from the corresponding Stratix BSDL files ...
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... HardCopy II devices. Device HC210W HC210 HC220 HC230 HC240 IDCODE (32 Bits) Part Number (16 Bits) 0010 0000 1100 0001 0010 0000 1100 0010 0010 0000 1100 0011 0010 0000 1100 0100 0010 0000 1100 0101 IDCODE is always 1 ...
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HardCopy Series Handbook, Volume 1 BSDLCustomizer is a TCL script which is used to modify the BSDL file’s port definitions and boundary-scan chain groups’ attributes according to the design and pin assignments from the Quartus II software PIN file. Once ...
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Table 3–4. HardCopy II JTAG Timing Parameters and Values (Part ...
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HardCopy Series Handbook, Volume 1 Table 3–5. Document Revision History (Part Date and Document Version May 2005, v2.0 Updated Table 3-2. January 2005 Added document to the HardCopy Series Handbook. v1.0 3–6 Preliminary Changes Made Summary of ...
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H51018-3.3 Introduction This chapter provides preliminary information on absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for HardCopy Absolute HardCopy II devices are offered in both commercial and industrial grades. All parameter limits are representative of ...
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HardCopy Series Handbook, Volume 1 Table 4–2. Maximum Duty Cycles in Voltage Transitions Recommended Table 4–3 operating conditions. Operating Conditions Table 4–3. HardCopy II Device Recommended Operating Conditions Symbol Parameter V Supply voltage for internal CCINT logic and input buffers ...
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... HC220 T = 25° C HC230 J HC240 V = ground, no HC210W I load, no toggling HC210 inputs HC220 T = 25° C HC230 3.3 V CCPD HC240 DC Electrical Characteristics Note (1) (Part Minimum Maximum Unit 0 85 -40 100 is not ramped up within this specified Table 4–2 based upon the input duty cycle. ...
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... High-level input voltage IH V Low-level input voltage IL V High-level output voltage OH 4–4 Note (1) Conditions Device Minimum Typical Maximum V = ground, no HC210W I load, no toggling HC210 inputs HC220 T = 25° C HC230 J HC240 3.3 V — I CCIO 2.5 V — I CCIO 1.8 V — I CCIO 1.8 V — ...
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Table 4–5. LVTTL Specifications (Part Symbol Parameter V Low-level output voltage OL Notes to Table 4–5: (1) HardCopy II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B. (2) ...
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HardCopy Series Handbook, Volume 1 Table 4–7. 2.5-V I/O Specifications (Part Symbol Parameter V Low-level output voltage OL Notes to Table 4–7: (1) HardCopy II devices V voltage-level support of 2.5 ± -5% is narrower than defined ...
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Table 4–9. 1.5-V I/O Specifications (Part Symbol Parameter V Low-level output voltage OL Notes to Table 4–9: (1) HardCopy II devices V voltage-level support of 1.5 ± -5% is narrower than defined in the normal range of ...
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HardCopy Series Handbook, Volume 1 Figure 4–2. Transmiter Output Waveforms for Differential I/O Standards Single-Ended Waveform Differential Waveform (Mathematical Function of Positive & Negative Channel) Table 4–10. 2.5-V LVDS I/O Specifications Symbol Parameter V I/O supply voltage for I/O banks ...
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Table 4–11. 3.3-V LVDS I/O Specifications Symbol Parameter V Output and feedback pins in PLL CCIO banks 9, 10, 11, and 12 V Input differential voltage swing ID (single-ended) V Input common mode voltage ICM V Output differential voltage OD ...
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HardCopy Series Handbook, Volume 1 Table 4–12. LVPECL Specifications (Part Symbol Parameter R Receiver differential input L discrete resistor (external to HardCopy II devices) Notes to Table 4–12: (1) Like Stratix II devices, LVPECL is supported by ...
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Table 4–14. 3.3-V PCI Specifications Symbol Parameter V Output-supply voltage CCIO V High-level input voltage IH V Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL Table 4–15. PCI-X Mode 1 Specifications Symbol Parameter V ...
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HardCopy Series Handbook, Volume 1 Table 4–16. SSTL-18 Class I Specifications (Part Symbol Parameter V Low-level output voltage OL Notes to Table 4–16: (1) This specification is supported across all the programmable drive settings available for this ...
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Table 4–18. SSTL-18 Differential Specifications (Part Symbol Parameter V AC differential input cross point X(AC) voltage V AC differential input voltage SWING(AC) V Input clock signal offset voltage ISO ΔV Input clock signal offset voltage ISO variation ...
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HardCopy Series Handbook, Volume 1 Table 4–20. SSTL-2 Class II Specifications Symbol Parameter V Output-supply voltage CCIO V Termination voltage TT V Reference voltage REF V High-level input voltage IH (DC) V Low-level input voltage IL (DC) V High-level input ...
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Table 4–22. 1.5-V HSTL Class I Specifications Symbol Parameter V Output-supply voltage CCIO V Input reference voltage REF V Termination voltage high-level input voltage IH (DC low-level input voltage IL (DC high-level input ...
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HardCopy Series Handbook, Volume 1 Table 4–23. 1.5-V HSTL Class II Specifications (Part Symbol Parameter V Low-level output voltage OL Notes to Table 4–23: (1) This specification is supported across all the programmable drive settings available for ...
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Table 4–25. 1.8-V HSTL Class I Specifications (Part Symbol Parameter V Low-level output voltage OL Notes to Table 4–25: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown ...
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HardCopy Series Handbook, Volume 1 Table 4–27. 1.8-V Differential HSTL Specifications (Part Symbol Parameter V AC differential input voltage DIF (AC differential cross point voltage OX (AC) Bus Hold Table 4–28 specifications. Specifications Table 4–28. ...
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On-Chip Table 4–29 when using series or differential on-chip termination for HC210W Termination devices only. Specifications Table 4–29. Series On-Chip Termination Specification for I/O Banks Supporting Memory Interface IOEs for HC210W Notes (1), (2), (3) Symbol Description 25 Ω R ...
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... The resistance tolerances for calibrated SOCT and POCT are at the time of initial calibration. If the temperature or voltage changes over time, the tolerance may also change. (3) This table applies only to HC210, HC220, HC230 and HC240 devices. 4–20 and 4–31 define the specification for internal termination ...
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... The resistance tolerances for calibrated SOCT and POCT are at the time of initial calibration. If the temperature or voltage changes over time, the tolerance may also change. (4) This table applies only to HC210, HC220, HC230, and HC240 devices. Pin Capacitance Table 4–32 Table 4–32. HardCopy II Device Capacitance ...
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... Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within ± 0.5 pF. Maximum Input Tables 4–33 HardCopy II I/Os. Clock Rates Table 4–33. HardCopy II Maximum Input Clock Rates of HC210, HC220, HC230 and HC240 Devices (Part Memory I/OStandard Interface IOEs LVTTL 500 2 ...
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... Table 4–33. HardCopy II Maximum Input Clock Rates of HC210, HC220, HC230 and HC240 Devices (Part Memory I/OStandard Interface IOEs PCI-X (1) 500 Differential SSTL2 class I 500 (2), (3) Differential SSTL2 class II 500 (2), (3) Differential SSTL18 class I 500 (2), (3) Differential SSTL18 class II 500 (2), (3) 1 ...
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HardCopy Series Handbook, Volume 1 Table 4–34. HardCopy II Maximum Input Clock Rates of HC210W Devices I/O Standard LVTTL 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVTTL/LVCMOS LVCMOS SSTL2 class I SSTL2 class II SSTL18 class I SSTL18 class II 1.5-V HSTL ...
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... These numbers are preliminary and pending further silicon characterization. Maximum Tables 4–35 HardCopy II I/O's for all available drive strengths. Output Clock Rates Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices Note (1) (Part Memory Drive I/O Standard Interface ...
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... HardCopy Series Handbook, Volume 1 Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices Note (1) (Part Memory Drive I/O Standard Interface Strength IOEs 2.5 LVTTL / 8 mA LVCMOS (3) 1.8 LVTTL / 4 mA LVCMOS ( 1040 1 ...
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... Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices Note (1) (Part Memory Drive I/O Standard Interface Strength IOEs 1.8-V HSTL 4 mA class (3) 1.8-V HSTL 16 mA class (3) 1.5-V HSTL 4 mA class ...
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... HardCopy Series Handbook, Volume 1 Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices Note (1) (Part Memory Drive I/O Standard Interface Strength IOEs Differential 4 mA SSTL18 class ( (3) Differential 8 mA SSTL18 class (5) ...
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... Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices Note (1) (Part Memory Drive I/O Standard Interface Strength IOEs 1.5-V differential 16 mA HSTL class (5) ( Notes to Table 4–35: (1) The toggle rate applies output load for all I/O standards except for LVDS and HyperTransport technology on row I/O pins ...
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HardCopy Series Handbook, Volume 1 Table 4–36. HardCopy II Maximum Output Clock Rate for HC210W Devices Memory Drive I/O Standard Interface Strength 2.5 LVTTL / LVCMOS ( 1.8 LVTTL / ...
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Table 4–36. HardCopy II Maximum Output Clock Rate for HC210W Devices Memory Drive I/O Standard Interface Strength 1.8-V HSTL class (3) 1.8-V HSTL class ...
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HardCopy Series Handbook, Volume 1 Table 4–36. HardCopy II Maximum Output Clock Rate for HC210W Devices Memory Drive I/O Standard Interface Strength Differential 8 mA SSTL18 class 1.8-V differential 4 mA ...
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... Tables 4–37 HardCopy II I/Os using OCT. Table 4–37. HardCopy II Maximum Output Clock Rate for HC210, HC220, HC230 and HC240 Devices (OCT) Note (1) (Part Memory Drive I/O Standard Interface Strength IOEs OCT 50 Ω 3.3-V LVTTL OCT 50 Ω 2.5-V LVTTL OCT 50 Ω 1.8-V LVTTL OCT 50 Ω 3.3-V LVCMOS OCT 50 Ω ...
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... HardCopy Series Handbook, Volume 1 Table 4–37. HardCopy II Maximum Output Clock Rate for HC210, HC220, HC230 and HC240 Devices (OCT) Note (1) (Part Memory Drive I/O Standard Interface Strength IOEs OCT 50 Ω 1.5-V Differential (3) HSTL Class I Notes to Table 4–37: (1) The toggle rate applies output load for all I/O standards except for LVDS and HyperTransport technology on row I/O pins ...
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Table 4–38. HardCopy II Maximum Output Clock Rate for HC210W using OCT Memory Drive I/O Standard Interface Strength IOEs OCT 50 Ω Differential SSTL-2 Class I (3) OCT 25 Ω Differential SSTL-2 Class II (3) OCT 50 Ω Differential SSTL-18 ...
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HardCopy Series Handbook, Volume 1 Table 4–39. HighSpeed Timing Specifications and Definitions (Part HighSpeed Timing Specifications W t RISE t FALL Timing unit interval (TUI) f HSDR f HSDRDPA Channel-to-channel skew (TCCS) Sampling window (SW) Input jitter ...
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... The I/O differential buffer and input register do not have a minimum toggle rate. (5) Contact the Altera Applications Group for more information. Table 4–41 HC220, HC230 and HC240 HardCopy II devices. Table 4–41. HardCopy II High-Speed I/O Specifications for HC210, HC220, HC230 and HC240 Devices Note (1) (Part Symbol f (clock frequency) ...
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... HardCopy Series Handbook, Volume 1 Table 4–41. HardCopy II High-Speed I/O Specifications for HC210, HC220, HC230 and HC240 Devices Note (1) (Part Symbol f (data rate (LVDS, HyperTransport technology) HSDR (LVDS, HyperTransport technology) f (DPA data rate (LVDS, HyperTransport technology) HSDRDPA ...
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... Bandwidth ≤ 0.85 MHz Input or external feedback clock input jitter tolerance in terms of period jitter. Bandwidth > 0.85 MHz t Dedicated clock output period jitter OUTJITTER for HC210, HC220, HC230 and HC240 devices Dedicated clock output period jitter for HC210W device t External feedback compensation FCOMP ...
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... Frequency range where the clock SWITCHOVER switchover performs properly f PLL closed loop bandwidth CLKW f PLL VCO operating range for VCO HC210, HC220, HC230 and HC240 devices PLL VCO operating range for HC210W devices f Spread spectrum modulation SS frequency % spread Percent down spread for a given ...
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... Lower VCO frequency range for HC210W device f PLL output frequency to GCLK or RCLK OUT PLL output frequency to LVDS or DPA clock for HC210, HC220, HC230 and HC240 devices PLL output frequency to LVDS or DPA clock for HC210W devices f PLL clock output frequency to regular I/O pin ...
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... HardCopy II devices do not support PLL-based external memory interface except for SDR SDRAMs which do not require the DLL. (2) HC210W supports memory interface on the top I/O banks. (3) HC210 and HC220 support memory interface on the top I/O banks. HC230 and HC240 support memory interface on the top and bottom I/O banks. (4) You will need to under-clock a 300 MHz memory device. (5) You will need to under-clock a 250 MHz memory device ...
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Tables 4–45 the dedicated circuitry used for interfacing with external memory devices. Table 4–45. DLL Frequency Range Specifications Frequency Mode Table 4–46 HardCopy II DQS delay buffer. Multiply the number of delay buffers that you are using in the DQS ...
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... Peak-to-peak phase jitter on the phase shifted DDS clock (digital jitter is caused by DLL tracking). Delay stages used for requested DQS phase shift are reported in your project’s Compilation Report in the Quartus II software. Note (1) HC210, HC220, HC230 HC240 Stages (2 Table 4– ...
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Table 4–50. DQS Bus Clock Skew Adder Specifications (tDQS_CLOCK_SKEW_ADDER) Note to (1) Table 4–51. DQS Phase Offset Delay Per Stage Note to (1) Hot Socketing HardCopy II devices offer hot socketing, which is also known as hot plug-in or hot ...
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... Electrostatic Electrostatic discharge (ESD) protection is a design practice that is integrated in Altera FPGAs and structured ASIC devices. HardCopy II Discharge devices are no exception, and they are designed with ESD protection on all I/O and power pins. 4–46 and V ). For mixed-voltage environments, you can drive ...
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Figure 4–3 which will be used to explain ESD protection. Figure 4–3. Transistor-Level Diagram of HardCopy II Device I/O Buffers The CMOS output drivers in the I/O pins intrinsically provide electrostatic discharge protection. There are two cases to consider for ...
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HardCopy Series Handbook, Volume 1 The dashed line (see during a positive ESD zap. Figure 4–4. ESD Protection During Positive Voltage Zap When the I/O pin receives a negative ESD zap at the pin that is less than -0.7 V ...
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Details of ESD protection are also outlined in the Hot-Socketing and Power-Sequencing Feature and Testing for Altera Devices white paper located on the Altera website at www.altera.com. f For information on ESD results of Altera products, please see the ...
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HardCopy Series Handbook, Volume 1 4–50 Altera Corporation September 2008 ...
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... ASIC alternative to increasingly expensive Device Support multi-million gate ASIC designs. The HardCopy II design methodology offers a fast time-to-market schedule, providing ASIC designers with a solution to long ASIC development cycles. Using the Quartus software, you can leverage a Stratix seamlessly migrate your design to a HardCopy II device for production. ...
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HardCopy Series Handbook, Volume 1 Quartus II Features for HardCopy II Planning With the Quartus II software you can design a HardCopy II device using a Stratix II device as a prototype. The Quartus II software contains the following expanded ...
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HardCopy II In the Quartus II software, you have two methods for designing your Stratix II FPGA and HardCopy II companion device together in one Development Quartus II project. Flow ■ ■ Both of these flows are ...
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HardCopy Series Handbook, Volume 1 Figure 5–1. HardCopy II Flow in Quartus II Software Notes for (1) (2) Designing the Stratix II FPGA First The HardCopy II development flow beginning with the Stratix II FPGA prototype is very similar to ...
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Figure 5–2. Designing Stratix II Device First Flow Stratix II Prototype Device Development Phase In-System Verification HardCopy II Companion Device Development Phase Select a Larger HardCopy II Companion Design Submission & Back-End Implementation Phase Prototype your HardCopy II design by ...
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HardCopy Series Handbook, Volume 1 After you select your HardCopy II companion device, do the following: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ f For more information about the overall design flow using the Quartus II software, ...
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Figure 5–3. Designing HardCopy II Device First Flow HardCopy II Device Development Phase Stratix II Companion Device Development Phase In-System Verification Design Submission & Back-End Implementation Phase HardCopy II The HardCopy II Device Resource Guide compares the resources required to ...
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HardCopy Series Handbook, Volume 1 Figure 5–4. HardCopy II Device Resource Guide Use this report to determine which HardCopy II device is a potential candidate for migration of your Stratix II design. The HardCopy II device package must be compatible ...
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Table 5–1. HardCopy II Device Resource Guide Color Legend Color Package Resource The design can migrate to the Hardcopy II package and the design has been fitted with target device migration enabled in the Green HardCopy II Companion Device dialog ...
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... Stratix II EP2S130F1020 device. Based on the report, the HC230F1020 device in the 1,020-pin FineLine BGA is an appropriate HardCopy II device to migrate to. If the HC230F1020 device is not specified as a migration target during the compilation, its package and migration compatibility is rated orange, or Medium. The ...
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... You can also specify your HardCopy II companion device using the following tool command language (Tcl) command: set_global_assignment -name\ DEVICE_TECHNOLOGY_MIGRATION_LIST <HardCopy II Device Part Number> For example, to select the HC230F1020 device as your HardCopy II companion device for the EP2S130F1020C4 Stratix II FPGA, the Tcl command is: set_global_assignment -name\ ...
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... Software cases, you must remove certain settings in the design. This section explains the additional settings and constraints necessary for your design to be successful in both Stratix II FPGA and HardCopy II structured ASIC devices. Limit DSP and RAM to HardCopy II Device Resources On the Assignments menu, click Settings to view the Settings dialog box. ...
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For more information about the Design Assistant and the rules it uses, refer to the Design Guidelines for HardCopy Series Devices chapter of the HardCopy Series Handbook. To enable the Design Assistant to run during compilation, on the Assignment ...
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... The TimeQuest Timing Analyzer is a complete static timing analysis tool that you can use as a sign-off tool for Altera FPGAs and structured ASICs. Setting Up the TimeQuest Timing Analyzer If you want use TimeQuest for timing analysis, from the Assignments tab ...
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Use the following Tcl command to use TimeQuest as your timing analysis engine: set_global_assignment -name \ USE_TIMEQUEST_TIMING_ANALYZER ON You can launch the TimeQuest analyzer in one of the following modes: ■ ■ ■ In order to perform a thorough Static ...
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HardCopy Series Handbook, Volume 1 The derive_clock_uncertainty command applies inter-clock, intra-clock, and I/O interface uncertainties. This command automatically calculates and applies setup and hold clock uncertainties for each clock-to-clock transfer found in your design. In order to get I/O interface ...
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Altera strongly recommends that you use the derive_clock_uncertainty command in the HardCopy II revision. The HardCopy Design Center will not be accepting designs that do not have clock uncertainty constraint by either using the derive_clock_uncertainty command or the HardCopy II ...
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HardCopy Series Handbook, Volume 1 the floorplan. You must adjust the size and location of the LogicLock Regions you created in the HardCopy II device before compiling the design. f For information about using LogicLock Regions, refer to the Quartus ...
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For information about using Quartus II Incremental Compilation, refer to the Quartus II Incremental Compilation for Hierarchical and Team-Based Design chapter in volume 1 of the Quartus II Handbook. Maximum Fanout Assignments This feature is ...
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HardCopy Series Handbook, Volume 1 With the Altera significantly. When changes are made to your design as ECOs, you do not have to perform a full compilation in the Quartus II software. Instead, you would make changes directly to the ...
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A partial list of examples of this type are as follows: ■ ■ ■ ■ Migrating Changes that must be Implemented Differently Some changes must be implemented differently on the two architectures. Changes affecting the logic of the design may ...
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... Change Type The basic creation and deletion is the same on both architectures. However, as with LC_COMB creation and deletion, the location of an LC_FF in a HardCopy II revision has no meaning in the Stratix II revision and vice versa. Because a Stratix II LCELL_COMB atom may have ...
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If testing identifies problems requiring ECO changes, equivalent changes can be applied to both Stratix II and HardCopy II revisions, as described in the next section. Applying ECO Changes The general flow for applying equivalent changes in companion revisions is ...
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HardCopy Series Handbook, Volume 1 The Tcl command for running the HardCopy II Assembler is as follows: execute_module -tool asm -args "-- read_settings_files=\ off --write_settings_files=off" The Tcl command for the HardCopy II Netlist Writer is as follows: execute_module -tool cdb ...
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For more information about using the Cadence Encounter Conformal verification software, refer to the Cadence Encounter Conformal Support chapter in volume 3 of the Quartus II Handbook. HardCopy II The HardCopy II Utilities menu in the Quartus II software ...
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HardCopy Series Handbook, Volume 1 Each of the features within HardCopy II Utilities is summarized in Table following sections. Table 5–4. HardCopy II Utilities Menu Options Menu Description Create/Overwrite Create a new companion HardCopy II revision or update an existing ...
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The Quartus II software creates specific HardCopy II design revisions of the project in conjunction to the regular project revisions. These parallel design revisions for HardCopy II devices are called companion revisions. 1 When you have successfully compiled your Stratix ...
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HardCopy Series Handbook, Volume 1 Figure 5–11. Set Current HardCopy II Companion Revision Compiling the HardCopy II Companion Revision The Quartus II software allows you to compile your HardCopy II design with preliminary timing information. The timing constraints for the ...
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... Altera uses the companion revisions in a single Quartus II project to maintain the seamless migration of your design from a Stratix II FPGA to a HardCopy II structured ASIC. This methodology allows you to design with one set of Register Transfer Level (RTL) code to be used in both Stratix II FPGA and HardCopy II structured ASIC, guaranteeing functional equivalency ...
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HardCopy Series Handbook, Volume 1 utility generates. This archive contains only the necessary data from the Quartus II project needed to implement the design in the HardCopy Design Center. In order to use the Archive HardCopy II Handoff Files utility, ...
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The HardCopy II Advisor shows the necessary steps that pertain to your current selected device. The Advisor shows a slightly different view for a design with Stratix II selected as compared to a design with HardCopy II selected. In the ...
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HardCopy Series Handbook, Volume 1 Figure 5–13 selected. Figure 5–13. HardCopy II Advisor with Stratix II Selected Figure 5–14 selected. Figure 5–14. HardCopy II Advisor with HardCopy II Device Selected 5–32 shows the HardCopy II Advisor with the Stratix II ...
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... You can see the placement of a DSP block constructed of HCell Macros, various logic HCell Macros, and an M4K memory block. A labeled close-up view of this region is shown in Altera Corporation September 2008 shows an example of the HC230F1020 device floorplan. Figure HardCopy II Utilities Menu 5–16. 5–33 ...
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... Quartus II software provide you with the tools necessary to complete your Stratix II FPGA prototype and HardCopy II structured ASIC design. The addition of the HardCopy II companion revisions feature to the process allows for rapid development and verification that your HardCopy II design is functionally equivalent to your Stratix II FPGA prototype. 5– ...
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Document Table 5–5 Revision History Table 5–5. Document Revision History Date and Document Version September 2008, Updated chapter number and metadata. v2.5 June 2007 v2.4 Updated with the current Quartus II software version 7.1 information. December 2006 Minor updates for ...
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HardCopy Series Handbook, Volume 1 5–36 Altera Corporation September 2008 ...
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H51025-1.3 Introduction The Quartus many of which support an interactive Tcl shell. Using the Tcl shell, you can perform FPGA or HardCopy Quartus This chapter provides an introduction to Tcl operations for script-based HardCopy II design using the interactive Tcl ...
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... The interactive Tcl shell supports Tcl version 8.4. Table 6–1. Quartus II Command-Line Executables with Interactive Tcl Support Executable Name quartus_sh A basic Tcl interpreter shell. Supports assignment specification, compile operations, and native operating system commands. For more information, refer to Command-Line Executables section of the Quartus II Scripting Reference Manual. quartus_sta The Quartus II TimeQuest timing analyzer engine supports building the timing graph for the design and timing analysis Tcl commands ...
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... The interactive Tcl shell for command-line executables is invoked using the -s command-line switch. For example, to run the basic Quartus shell, type quartus_sh -s at the command prompt: % quartus_sh -s Info: *********************************************************************** Info: Running Quartus II Shell Info: *********************************************************************** Info: The Quartus II Shell supports all TCL commands in addition Info: to Quartus II Tcl commands. All unrecognized commands are Info: assumed to be external and are run using Tcl's " ...
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HardCopy Series Handbook, Volume 1 Table 6–2. Tcl Package Support in Quartus II Executables Executable Name Supported Tcl Package quartus_sh quartus_tan quartus_cdb quartus_sim A brief description of each of the Tcl packages referenced in given find out ...
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Table 6–3. Quartus II Tcl Package Descriptions Tcl Package advanced_timing Traverse the timing netlist and get information about timing modes. backannotate Back annotate assignments. chip_editor Identify and modify resource usage and routing with the Chip Editor. database_manager Manage version-comparable database ...
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HardCopy Series Handbook, Volume 1 This example shows what is, perhaps, the simplest way to execute the HardCopy II design flow. If you have developed and applied the design I/O, location and timing constraints for the project, these constraints are ...
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Figure 6–1. The HardCopy II Design Flow Source .v, .vhd, .tdf .edf, .bdf Design Files Signal-Pin Assignment Tcl Files Timing Constraint Tcl Files Compile Stratix II Prototype Compilation Report Files Verify the Stratix II Prototype Compare Design ...
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HardCopy Series Handbook, Volume 1 The design flow of design and migrates this design to a HardCopy II device target, or begins with a HardCopy II target and migrates this design to a Stratix II target for FPGA prototyping. The ...
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Tcl command is executed: tcl> project_new demo_design Creating a new project creates a quartus settings file (QSF) and a ...
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HardCopy Series Handbook, Volume 1 New Project Example Script The following script shows the use of Tcl commands for opening and closing a project called demo_design with the revision name, demo_design_fpga. If the project does not already exist ...
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Making Global Initializing a HardCopy II Design Assignments For a HardCopy II design, the following key operations are required after a Quartus II project is created: ■ ■ ■ ■ ■ In addition to these, other project settings affecting downstream ...
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HardCopy Series Handbook, Volume 1 The key global variables for a HardCopy II project are listed in Table 6–4. Key HardCopy II Design Settings Global Variable Name <name> VERILOG_FILE VHDL_FILE AHDL_FILE EDIF_FILE BDF_FILE FAMILY DEVICE TOP_LEVEL_ENTITY DEVICE_TECHNOLOGY_MIGRATION_LIST COMPANION_REVISION ENABLE_DRC_SETTINGS USE_TIMEQUEST_TIMING_ANALYZER ...
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The DEVICE and DEVICE_TECHNOLOGY_MIGRATION_LIST variables are the parts used for the Stratix II prototype design and the HardCopy II design. The selected Stratix II prototype device must be compatible with the selected HardCopy II device to make migration possible. Valid ...
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... Table 6–5. Stratix II Prototype Options for HardCopy II The following two Tcl commands demonstrate setting the DEVICE and DEVICE_TECHNOLOGY_MIGRATION_LIST variables. tcl> set_global_assignment -name DEVICE EP2S90F1020C4 tcl> set_global_assignment -name \ 6–14 HardCopy II Part HC230F1020C HC2401020C HC240F1508C DEVICE_TECHNOLOGY_MIGRATION_LIST HC230F1020C (Part Stratix II Prototype Part EP2S90F1020C3 EP2S90F1020C4 EP2S90F1020C5 EP2S90F1020I4 EP2S130F1020C3 EP2S130F1020C4 EP2S130F1020C5 ...
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The Design Assistant You should turn on the Design Assistant at the beginning of the design process by turning on the ENABLE_DRC_SETTINGS global variable. tcl> set_global_assignment \ The Design Assistant runs concurrently with every step of both the prototype Stratix ...
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... The example Tcl script below illustrates the application of global constraints for a HardCopy II project. ## Example Global Assignments Script for a HardCopy II Design ## This Script Applies Settings for a EP2S90 Stratix II ## prototype FPGA target and a HC230 HardCopy II target ## Source Design File Settings ## =========================== set_global_assignment -name VERILOG_FILE demo_design.v set_global_assignment -name VERILOG_FILE example_ram ...
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Making I/O Because of the complex rules governing the use of programmable I/O cells and their availability for specific pins and packages, Altera highly Assignments recommends that I/O assignments are completed using the Pin Planning tool and the Assignment Editor ...
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HardCopy Series Handbook, Volume 1 The assignment name, <name>, should be set to IO_STANDARD to indicate that an I/O specification is being applied. The related I/O signal is specified as -to <destination>. The destination argument is a string providing details ...
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You can specify a number of other I/O parameters by using the set_instance_assignment command. Some of the more common parameters are listed in Table 6–7. Tcl Common I/O Parameter Settings <name> setting weak_pull_up_resistor output_pin_load fast_output_register fast_output_enable_register fast_input_register current_strength_new stratixii_termination f ...
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HardCopy Series Handbook, Volume 1 I/O Assignment Example Script The following Tcl script example specifies several different I/O constraints. ## Signal-Ball Assignments set_location_assignment PIN_AH5 -to addr_out[0] set_location_assignment PIN_AH6 -to addr_out[1] set_location_assignment PIN_AJ5 -to data_in[0] set_location_assignment PIN_AJ6 -to data_in[1] set_location_assignment PIN_AJ32 ...
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... For more information on timing constraints, refer to the Timing Analysis section in volume 3 of the Quartus II Handbook. Specifying System Clocks The most basic constraints that should be applied describe the clock for each clock domain. Parameters usually specified for each clock are: ■ ■ ...
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HardCopy Series Handbook, Volume 1 set_clock_uncertainty -to clk_a 0.25 create_clock -period 10.0 -name clk_b [get_ports clk_b] set_clock_latency -source -late 4.0 clk_b set_clock_latency -source -early 3.0 clk_b set_clock_uncertainty -to clk_b 0.25 Input/Output Timing System clock parameters define the setup and hold ...
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As an example, the following Tcl script specifies input and output min and max delays for two I/O signals. Input data_in[0] has minimum and maximum external delays and 7 ns, respectively. Output data_out[0] has minimum and maximum ...
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HardCopy Series Handbook, Volume change these default settings, refer to the Timing Settings section in the Quartus II Support of HardCopy Series Devices chapter in volume 1 of the Quartus II Handbook. In TimeQuest, the constraint set_false_path ...
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Example of Classic Timing Analyzer Tcl Script # Timing Assignments # ================== create_base_clock –fmax 100 MHz –target ref_clk ref_clk set_instance_assignment -name LATE_CLOCK_LATENCY 3ns -to ref_clk set_instance_assignment -name EARLY_CLOCK_LATENCY 2ns -to ref_clk set_clock_uncertainty –hold –to ref_clk 0.250ns set_clock_uncertainty –setup –to ref_clk ...
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HardCopy Series Handbook, Volume 1 The switches relevant to prototype Stratix II and HardCopy II design are listed in Table 6–8. execute_flow Tcl Command Switches Switch analysis_and_elaboration attempt_similar_placement check_ios check_netlist compile compile_and_simulate early_timing_estimate eco export_database fast_model generate_functional_sim_netlist import_database 1 The ...
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The Design Assistant and Timing constraint checks are run if they are enabled in the Quartus II Settings file. You should check I/O assignments to avoid problems in downstream compile operations this, the execute_flow compilation is broken into ...
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HardCopy Series Handbook, Volume 1 This command initializes the database for the HardCopy II revision and creates a new QSF file (in this example, demo_design_hcii.qsf), ensuring that all constraints for the Stratix II FPGA revision are ported over. Next, the ...
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Table 6–9. Stratix II Compile Report File Descriptions Switch Tool <revision>.upc.rpt Timing Constraint Checker <revision>.asm.rpt Assembler <revision>.rec.rpt Companion Revision Comparison <revision>.flow.rpt Flow <revision>.sta.rpt TimeQuest Comparing Before submitting the HardCopy II project to the Altera Design Center, it should be checked ...
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... Passed (0/0) ; Passed (5/5) ; Passed (130/130) ; Passed (1020/1020) ; Passed (1/1) ; Passed (2/2) ; Passed (3/3) ; Passed (10/10) ; Passed (100/100) ; Passed (8/8) ; Passed (335084/335084) ; Passed (1/1) Use the execute_module -tool sta Tcl command to run a timing analysis Tcl script in quartus_sta from within the basic quartus shell, quartus_sh ...
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... Run the quartus_sta interactive Tcl shell independently and execute Tcl commands and scripts at the Tcl prompt. Use the execute_module -tool tan Tcl command to run a timing analysis Tcl script in quartus_tan from within the basic quartus shell, quartus_sh. Run the quartus_tan interactive Tcl shell independently and execute Tcl commands and scripts at the Tcl prompt ...
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HardCopy Series Handbook, Volume 1 HardCopy II The following script draws together the Tcl ideas discussed thus far into a top-level Tcl script for the quartus_sh Tcl shell. This script implements Example Tcl a HardCopy II design called demo_design. It ...
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... DEVICE EP2S90F1020C4 set_global_assignment -name TOP_LEVEL_ENTITY demo_design ## HardCopy II Companion Revision and Target Settings ## ================================================== set_global_assignment -name COMPANION_REVISION_NAME \ demo_design_hardcopyii set_global_assignment -name DEVICE_TECHNOLOGY_MIGRATION_LIST HC230F1020 ## Design Assistant Assignments and Settings Required for HardCopy II ## ================================================================== set_global_assignment -name ENABLE_DRC_SETTINGS ON set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name REPORT_IO_PATHS_SEPARATELY ON ## The following assignments are Classic Timing Analyzer only and ## are not used by TimeQuest ...
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HardCopy Series Handbook, Volume 1 set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON set_global_assignment -name ENABLE_CLOCK_LATENCY ON ## End of global_assignments.tcl Pin Assignments Script pin_assignments.tcl The pin_assignments.tcl script run from the top-level script, demo_design.tcl, specifies top-level design signal to package ball assignments and I/O ...
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Output delay of 6ns (max) & 2ns (min) for bus data_out[1:0] set_output_delay –clock ref_clk –max 6 [get_ports data_out] set_output_delay –clock ref_clk –min 2 [get_ports data_out] # Don’t care about timing on the ...
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HardCopy Series Handbook, Volume 1 Document Table 6–10 Revision History Table 6–10. Document Revision History Date and Document Version September 2008, Updated chapter number and metadata. v1.3 June 2007, v1.2 Minor text edits. December 2006 Updates for the Quartus II ...
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... HardCopy II design flow will soon be mandatory. The TimeQuest timing analyzer is a complete static timing analysis tool that you can use as a sign-off tool for Altera FPGAs and structured ASICs. As FPGA devices become denser and faster, they are the targets of complex designs and applications that previously were implemented in ASICs ...
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... HardCopy II versus Stratix II Timing The back-end design of your HardCopy II structured ASIC includes timing closure in accordance with the timing specification achieved in the Quartus II software for the Stratix II FPGA prototype and HardCopy II device. However, you should be aware that this does not mean that actual path timing in the Stratix II FPGA is duplicated in the HardCopy II device ...
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ALMs in Stratix II devices to fine-grain HCell macros in HardCopy II devices. All ALM functions are re-mapped to HCells in HardCopy II devices. Using fine-grain HCells eliminates the need for the programmable routing multiplexers (MUXs) found inside the ...
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... HardCopy II mean that insertion delays, latencies, skew characteristics, jitter, and PLL compensation are different from the Stratix II FPGA. The effect of this is described in the section. Clock Distribution Effects The HardCopy II structured ASIC has a clock distribution scheme that is similar to that in Stratix II FPGAs with some notable differences: ■ ■ ■ ...
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... HardCopy II devices. The Quartus II software implements compensation delays for PLLs in your HardCopy II device to account for differences in PLL clock distribution. This ensures that the compensation modes used in the Stratix II FPGA are also used in the HardCopy II structured ASIC. HardCopy II To achieve timing closure for your HardCopy II structured ASIC ...
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HardCopy Series Handbook, Volume 1 Altera recommends you use the TimeQuest timing analyzer. You can specify that the TimeQuest timing analyzer be used by the Quartus II software rather than the default Classic Timing Analyzer. The TimeQuest timing analyzer validates ...
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Figure 7–1. Stratix II First Timing Closure Flow Note to Figure 7–1: (1) Timing constraints are required in Stratix II revision and HardCopy II revision. The TimeQuest timing analyzer supports industry-standard SDC files (.sdc) and Classic Timing Analyzer supports Quartus ...
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HardCopy Series Handbook, Volume 1 software can generate static timing analysis scripts for use in Synopsys PrimeTime tools. In addition, timing can be further verified in third-party, timing-driven simulation tools. When software timing verification of the Stratix II prototype FPGA ...
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The TimeQuest timing analyzer provides a number of timing checks during the HardCopy II design flow. The HardCopy II Advisor guides you to launch the TimeQuest timing analyzer for these timing checks and ensures that the design is fully constrained, ...
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HardCopy Series Handbook, Volume 1 specification, as provided in the sdc package. Quartus II software returns warning messages in the early stage of the compilation for HardCopy II design flow if the SDC file contains any constraints that use commands ...
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For more detailed information about the features and capabilities of the TimeQuest timing analyzer, refer to the TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook. Using Classic Timing Analyzer Classic Timing Analyzer analyzes the delay ...
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HardCopy Series Handbook, Volume 1 Figure 7–4. Classic Timing-Related Settings in the HardCopy II Advisor Classic Timing Analyzer, unlike the TimeQuest timing analyzer, supports some timing constraints that are incompatible with the HardCopy II design. In the HardCopy II Advisor, ...
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Figure 7–5. Classic Timing Analyzer Unsupported Timing Assignments in HardCopy II Advisor Altera Corporation September 2008 HardCopy II Timing Closure Methodology 7–13 ...
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HardCopy Series Handbook, Volume 1 The Compilation Report for both the Stratix II and HardCopy II revisions of your project includes a Timing Constraints Check section (Figure coverage provided by the timing constraints used in the design. You should examine ...
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FPGA and HardCopy revisions in the flow. If you do not do this, you cannot determine whether the HardCopy series device meets the required timing of the end ...
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HardCopy Series Handbook, Volume 1 Figure 7–7. Clock Attributes The clock settings for PLL clocks are derived automatically based on the PLL settings and reference clock characteristics. You can also override the default PLL clock settings for timing analysis by ...
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For a full list of available report APIs, refer to the SDC and TimeQuest API Reference Manual. Primary Input Port Timing You must specify the primary input port timing constraint for every primary input port in the design (and ...
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HardCopy Series Handbook, Volume 1 Figure 7–9. Internal Input Delay Specification (Setup) data clk Figure 7–10 Figure 7–10. Internal Input Delay Specification (Hold) data clk Primary Output Port Timing You must specify the output port timing constraint for every primary ...
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External Output Delay Specification One way to capture output port timing is to describe the external timing environment, which is the maximum and minimum delay times of external signals that are driven by the primary output ports of the HardCopy ...
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HardCopy Series Handbook, Volume 1 Combinational Timing In combinational timing circuits, a path exists from a primary input port to a primary output port. This type of circuit does not contain any registers. Therefore, it does not require a clock ...
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Unsupported HardCopy II Timing Constraints for Classic Timing Analyzer Unsupported The Quartus II software supports a wide variety of complex timing constraints. When using Classic Timing Analyzer for HardCopy II HardCopy II design, however, some of these constraints are not ...
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... Quartus II software and subsequent transfer to the Altera HardCopy Design Center for the back-end design of your structured ASIC. Following the recommendations in this chapter will help ensure success in your HardCopy II project. ...
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Document Table 7–2 Revision History Table 7–2. Document Revision History Date and Document Version September 2008, Updated chapter number and metadata. v2.2 June 2007, v2.1 Minor text edits. December 2006 Major updates for the Quartus II software version 6.1.0 v2.0 ...
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HardCopy Series Handbook, Volume 1 7–24 Altera Corporation September 2008 ...
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H51024-1.4 Introduction Altera manufactured on a 1.2-V, 90-nm process technology and offer many similar features. Designers can use the Quartus their Stratix II design to a HardCopy II device. The Quartus II software ensures that the design revision targeting a ...
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... Settings dialog box. For example, if your design targets the EP2S130 device in the 1,020-pin FineLine BGA provides the EP2S90 and EP2S180 devices in the 1,020-pin FineLine BGA package as migration options as well as the HC230 device in the 1,020-pin FineLine BGA package. Conversely, the HardCopy II architecture allows you to design a structured ASIC and then prototype with a wide range of Stratix II devices ...
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... EP2S90 EP2S130 EP2S130 EP2S180 lists the available HardCopy II and Stratix II companion pairs. Package HardCopy II Device HC210 HC210 HC210 HC220 HC220 HC220 HC230 HC230 1,020 Pins 1,508 Pins HC240 HC240 EP2S180 EP2S180 Companion Pair Stratix II Device EP2S30 EP2S60 EP2S90(2) EP2S60 EP2S90 EP2S130 ...
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... I/O Pins Blocks Logic (3) 360K 334 144 720K 334 190 1 M 308 190 720K 492 255 1 M 494 408 Companion Pair Stratix II Device HC230 EP2S180 HC240 EP2S180 HC240 EP2S180 Note (1) M-RAM Total 18 × 18 Blocks RAM Bits Multipliers 0 663,552 64 0 875,520 144 0 875,520 ...
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... HC220 FineLine BGA EP2S90 1,020-pin 36,384 HC230 FineLine BGA EP2S130 1,020-pin 53,016 HC230 FineLine BGA EP2S180 1,020-pin 71,760 HC230 FineLine BGA EP2S180 1,020-pin 71,760 HC240 FineLine BGA EP2S180 1,508-pin 71,760 HC240 FineLine BGA Notes to Table 8–3: (1) Table 8–3 does not include the HC210W device. For information on the HC210W device, contact the Altera Applications Group ...
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... The I/O pin counts for all HC230 combinations include four dedicated fast PLL clock inputs (FPLL7CLKp/n, FPLL8CLKp/n) that can be used for data inputs. (4) The I/O pin counts for HC240 combinations include eight dedicated fast PLL clock inputs (FPLL7CLKp/n, FPLL8CLKp/n, FPLL9CLKp/n, and FPLL10CLKp/n) that can be used for data inputs ...
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... The top I/O banks 3 and 4 are memory interface IOEs on all HardCopy II devices. The bottom I/O banks 7 and 8 are general purpose IOEs on HC210 and HC220 but memory interface IOEs on HC230 and HC240 devices. The general purpose IOEs on the bottom of the device support PCI clamping, but the general purpose IOEs on the right side do not. ...
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HardCopy Series Handbook, Volume 1 Figure 8–1. HardCopy II HC240 I/O Banks PLL 7 Memory Interface IOEs Bank 2 High-Speed IOEs I/O Banks 1 & 2 Support 3.3-, PLL 1 2.5- & 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS & PLL 2 ...
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... The I/O pin counts for all HC230 combinations include four dedicated fast PLL clock inputs (FPLL7CLKp/n, FPLL8CLKp/n) that can be used for data inputs. (4) The I/O pin counts for HC240 combinations include eight dedicated fast PLL clock inputs (FPLL7CLKp/n, FPLL8CLKp/n, FPLL9CLKp/n, and FPLL10CLKp/n) that can be used for data inputs ...
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... Similar to Stratix II devices, these I/O standards are only available on input clock pins, output clock pins in I/O banks 9, 10, 11, 12, and DQS pins in top I/O banks 3, 4 for all HardCopy II devices, and DQS pins in bottom I/O banks 7 and 8 for HC230 and HC240 devices. (3) Pseudo-differential HSTL and SSTL inputs only use the positive polarity input in the speed path. The negative input is not connected internally ...
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Table 8–7 Table 8–7 pins. Table 8–7. Hardcopy II Supported I/O Standards of Input Clocks, Clock Out, and PLL Feedback (Part I/O Standard Type 3.3-V LVTTL / Single- 3.3/2.5 LVCMOS ended 2.5-V LVTTL / Single- 3.3/2.5 ...
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... Notes to Table 8–7: CLK8 and CLK10 pins on HC210, HC220, and HC230 devices do not support differential standards LVDS and (1) HyperTransport technology. Only LVTTL is supported on these CLK pins for these devices. CLK[4..7] pins on HC210 and HC220 devices do not support SSTL, HSTL, differential SSTL, and HSTL input or (2) output ...