GAL16LV8D-5LJ Lattice Semiconductor Corp., GAL16LV8D-5LJ Datasheet
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GAL16LV8D-5LJ
Manufacturer Part Number
GAL16LV8D-5LJ
Description
Manufacturer
Lattice Semiconductor Corp.
Datasheets
1.GAL16LV8.pdf
(22 pages)
2.GAL16LV8C-15LJ.pdf
(22 pages)
3.GAL16LV8C-15LJ.pdf
(22 pages)
Specifications of GAL16LV8D-5LJ
Case
PLCC
Date_code
0431+
Available stocks
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Price
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LAT
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GAL16LV8D-5LJ
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Lattice Semiconductor Corporation
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10 000
• HIGH PERFORMANCE E
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
• E
• EIGHT OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
The GAL16LV8D, at 3.5 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL16LV8C can interface with both 3.3V and 5V
signal levels. The GAL16LV8 is manufactured using Lattice
Semiconductor's advanced 3.3V E
bines CMOS with Electrically Erasable (E
High speed erase times (<100ms) allow the devices to be repro-
grammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 archi-
tecture as its 5V counterpart and supports all architectural features
such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
16lv8_05
Features
Description
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 2.5 ns Maximum from Clock Input to Data Output
— UltraMOS
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs
— I/O Interfaces with Standard 5V TTL Devices
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— 100% Functional Testability
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
(GAL16LV8C)
®
Advanced CMOS Technology
2
CMOS
2
®
CMOS process, which com-
TECHNOLOGY
2
) floating gate technology.
1
Functional Block Diagram
Pin Configuration
I/CLK
I
I
I
I
I
I
I
I
I
I
I
I
I
4
6
8
I
9
I
GND
GAL16LV8
2
I
Low Voltage E
Top View
I/CLK
PLCC
I/OE
11
Generic Array Logic™
GAL16LV8
I/O/Q
Vcc
20
8
8
8
8
8
8
8
8
CLK
I/O/Q
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
I/O/Q
13
18
14
16
2
CMOS PLD
OE
August 2004
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE