AGLN250V2-CSG81I Actel, AGLN250V2-CSG81I Datasheet

AGLN250V2-CSG81I

Manufacturer Part Number

AGLN250V2-CSG81I

Description

AGLN250V2-CSG81I

Manufacturer

Actel

Datasheet

1.AGLN060V2-ZVQG100I.pdf (132 pages)

Specifications of AGLN250V2-CSG81I

Lead_time

126

Pack_quantity

640

Comm_code

85423990

Current page: 1 of 132
Download datasheet (5Mb)

January 2010

IGLOO nano Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

Small Footprint Packages

Wide Range of Features

Reprogrammable Flash Technology

In-System Programming (ISP) and Security

Table 1 • IGLOO nano Devices

IGLOO nano Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os (packaged device)

Maximum User I/Os (Known Good Die)

Package Pins

Notes:

1. AGLN030 is available in the Z feature grade only.

2. AGLN030 and smaller devices do not support this feature

3. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.

4. For higher densities and support of additional features, refer to the

• nanoPower Consumption—Industry’s Lowest Power

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• Low-Power Active FPGA Operation

• Flash*Freeze Technology Enables Ultra-Low Power

• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze

• As Small as 3x3 mm in Size

• 10 k to 250 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design When Powered Off

• 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

• FlashLock

† AGLN030 and smaller devices do not support this feature.

UC/CS

QFN

VQFP

Consumption while Maintaining FPGA Content

Mode

Performance

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

to Secure FPGA Contents

2,3

AGLN010

QN48

UC36

10 k

260

1 k

–

AGLN015

QN68

15 k

128

384

1 k

–

UC81, CS81

AGLN020

High-Performance Routing Hierarchy

Advanced I/Os

Clock Conditioning Circuit (CCC) and PLL

Embedded Memory

Enhanced Commercial Temperature Range

QN68

20 k

172

520

• Segmented, Hierarchical Routing and Clock Structure

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

• Wide Range Power Supply Voltage Support per JESD8-B,

• Wide Range Power Supply Voltage Support per JESD8-12,

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

• True Dual-Port SRAM (except × 18 organization)

• –20°C to +70°C

1 k

–

IGLOO

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V

Allowing I/Os to Operate from 2.7 V to 3.6 V

Allowing I/Os to Operate from 1.14 V to 1.575 V

Capabilities, and External Feedback

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

QN48, QN68

and

UC81, CS81

AGLN030

VQ100

30 k

256

768

1 k

IGLOOe

–

handbooks.

AGLN060

VQ100

1,536

CS81

60 k

512

Yes

1 k

AGLN125

VQ100

125 k

1,024

3,072

CS81

Yes

1 k

Advance v0.8

†

AGLN250

VQ100

250 k

2,048

6,144

CS81

Yes

1 k

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