U1AFS600-FGG256 Actel, U1AFS600-FGG256 Datasheet
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U1AFS600-FGG256
Manufacturer Part Number
U1AFS600-FGG256
Description
Manufacturer
Actel
Specifications of U1AFS600-FGG256
Lead_time
77
Pack_quantity
90
Comm_code
85423990
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
U1AFS600-FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
U1AFS600-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
October 2008
© 2008 Actel Corporation
Actel Fusion Mixed-Signal FPGAs
for the MicroBlade Advanced Mezzanine Card Solution
Features and Benefits
High-Performance Reprogrammable Flash
Technology
Embedded Flash Memory
Integrated A/D Converter (ADC) and Analog I/O
On-Chip Clocking Support
MicroBlade Fusion Solutions
Fusion Devices
General Information
Memory
Analog and I/Os
Notes:
1. Refer to the
2. Refer to the
• Targeted to Advanced Mezzanine Card (AdvancedMC™)
• Designed in Partnership with MicroBlade
• 8051-Based Module Management Controller (MMC)
• Fully Compliant with PICMG AMC.0.R2.0 and IPMI v2.0
• AdvancedMC Reference Design and Starter Kit
• Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Nonvolatile, Retains Program when Powered Off
• Live at Power-Up (LAPU) Single-Chip Solution
• 350 MHz System Performance
• User Flash Memory – 2 Mbits to 8 Mbits
• 1 kbit of Additional FlashROM
• Up to 12-Bit Resolution and up to 600 ksps
• Internal 2.56 V or External Reference Voltage
• ADC: Up to 30 Scalable Analog Input Channels
• High-Voltage Input Tolerance: –10.5 V to +12 V
• Current Monitor and Temperature Monitor Blocks
• Up to 10 MOSFET Gate Driver Outputs
• ADC Accuracy is Better than 1%
• Internal 100 MHz RC Oscillator (accurate to 1%)
Designs
Specifications
– Configurable 8-, 16-, or 32-Bit Datapath
– 10 ns Access in Read-Ahead Mode
– P- and N-Channel Power MOSFET Support
– Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths
CoreMP7
Cortex-M1
System Gates
Tiles (D-flip-flops)
Secure (AES) ISP
PLLs
Globals
Flash Memory Blocks (2 Mbits)
Total Flash Memory Bits
FlashROM Bits
RAM Blocks (4,608 bits)
RAM kbits
Analog Quads
Analog Input Channels
Gate Driver Outputs
I/O Banks (+ JTAG)
Maximum Digital I/Os
Analog I/Os
datasheet for more information.
product brief for more information.
Low Power Consumption
In-System Programming (ISP) and Security
Advanced Digital I/O
SRAMs and FIFOs
• Crystal Oscillator Support (32 kHz to 20 MHz)
• Programmable Real-Time Counter (RTC)
• 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated
• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
• Sleep and Standby Low Power Modes
• Secure ISP with 128-Bit AES via JTAG
• FlashLock
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
• Single-Ended
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
• Hot-Swappable I/Os
• Programmable Output Slew Rate, Drive Strength, and Weak
• Pin-Compatible Packages across the Fusion Family
• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,
• True Dual-Port SRAM (except ×18)
• Programmable Embedded FIFO Control Logic
U1AFS25
PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz
3.3 V / 2.5 V /1.8 V / 1.5 V,
LVCMOS 2.5 V / 5.0 V Input
– Built-In I/O Registers
– 700 Mbps DDR Operation
Pull-Up/Down Resistor
and ×18 organizations available)
250,000
6,144
2 M
114
Yes
1 k
18
36
18
24
1
1
8
6
6
4
®
to Secure FPGA Contents
I/O
U1AFS600
600,000
13,824
4 M
172
Yes
108
1 k
10
18
24
10
30
40
Standards:
2
2
5
3.3 V PCI
Preliminary v0.4
/
LVTTL,
3.3 V PCI-X,
U1AFS1500
1,500,000
38,400
8 M
270
252
Yes
1 k
18
60
10
30
10
40
2
4
5
LVCMOS
and
®
I