TP2540N8 Supertex, TP2540N8 Datasheet
TP2540N8
Manufacturer Part Number
TP2540N8
Description
Manufacturer
Supertex
Specifications of TP2540N8
Case
SOT-89
Date_code
07+
Features
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Applications
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-G indicates package is RoHS compliant (‘Green’)
* MIL visual screening available.
Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
Ordering Information
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Operating and storage temperature
Soldering temperature*
Device
TP2540
Low threshold (-2.4V max.)
High input impedance
Low input capacitance (125pF max.)
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Complementary N and P-channel devices
Logic level interfaces - ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
TP2540N3-G
TO-92
TO-243AA (SOT-89)
Package Options
TP2540N8-G
P-Channel Enhancement Mode
Vertical DMOS FETs
-55°C to +150°C
+300°C
TP2540ND
Value
BV
BV
±20V
Die*
DGS
DSS
General Description
This low threshold enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and with the high input
impedance and positive temperature coeffi cient inherent
in MOS devices. Characteristic of all MOS structures,
this device is free from thermal runaway and thermally-
induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching
speeds are desired.
Pin Confi gurations
Product Marking
BV
TP5DW
DSS
-400
DRAIN
(V)
TO-92 (N3)
/BV
Y Y W W
2540
DGS
TP
TO-243AA (SOT-89) (N8)
SOURCE
W = Code for week sealed
GATE
YY = Year Sealed
WW = Week Sealed
R
(max)
TO-92 (N3)
DS(ON)
(Ω)
25
= “Green” Packaging
= “Green” Packaging
TO-243AA (SOT-89) (N8)
DRAIN
V
(max)
-2.4
GS(th)
(V)
GATE
DRAIN
TP2540
SOURCE
I
(min)
-0.4
D(ON)
(A)
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