SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet
SCD1283
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SCD1283 Summary of contents
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CD1283 IEEE 1284-Compatible Parallel Interface Product Features Parallel Port (Peripheral-side) High-speed, bidirectional, multi-protocol parallel port: Hardware implementation of all modes of the IEEE STD (Standard) 1284 specification (including automatic negotiation) — Centronics -compatible mode — Reverse Byte mode — Reverse ...
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Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express ...
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Contents 1.0 Overview ........................................................................................................................ 9 1.1 Advantages ........................................................................................................... 9 2.0 Conventions ...............................................................................................................11 3.0 Pin Information 3.1 Pin Diagram.........................................................................................................13 3.2 Pin List.................................................................................................................14 3.3 Pin Descriptions ..................................................................................................16 4.0 Register Summary 4.1 Register Summary Tables...................................................................................19 5.0 Functional Description 5.1 Device Architecture .............................................................................................22 5.2 ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 5.6.1 Compatibility Mode................................................................................. 40 5.6.2 Reverse-Nibble and Reverse-Byte Modes ............................................. 40 5.6.3 ID Request ............................................................................................. 41 5.6.4 ECP Mode.............................................................................................. 41 5.6.5 EPP Mode .............................................................................................. 41 5.7 Protocol Timing ................................................................................................... 41 5.8 General-Purpose I/O Port ...
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EPP Address Register............................................................................67 7.4.2 Input Value Register...............................................................................67 7.4.3 Manual Data Register.............................................................................68 7.4.4 Negotiation Enable Register...................................................................68 7.4.5 Negotiation Status Register....................................................................69 7.4.6 Ones Detect Register .............................................................................70 7.4.7 Output Value Register ............................................................................70 7.4.8 Parallel Channel Interrupt Enable Register ............................................71 7.4.9 Parallel Channel ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Figures 1 Functional Block Diagram ................................................................................... 10 2 Functional Block Diagram ................................................................................... 23 3 Internal Address Generation ............................................................................... 23 4 CD1283 Daisy-Chain Configuration .................................................................... 26 5 Interrupt Generation Logic .................................................................................. 28 6 Control Signal ...
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Revision History Revision Date 1.0 4/01 Datasheet IEEE 1284-Compatible Parallel Interface — CD1283 Description Initial release. 7 ...
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...
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Overview The CD1283 is a multi-function interface controller for printers, scanners, tape-drives, set-top boxes, data acquisition, and other applications that require high-speed, bidirectional, parallel communication with a host computer. All modes of the IEEE STD 1284 Standard Signaling Method ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Benefits • Multi-protocol bidirectional port for a wide range of applications. — Mbytes/sec. transfer rate — Provides future connectivity with new host systems • Reduces software complexity and guarantees specification compliance. ...
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Conventions Abbreviations Symbol C Hz Kbyte kHz k Mbyte MHz The use of ‘tbd’ indicates values that are ‘to be determined’, ‘n/a’ designates ‘not available’, and ‘N/C’ indicates a pin that is a ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Acronym IC integrated circuit IDC instruction and data cache ISA industry standard architecture LSB least-significant bit MPU microprocessing unit MSB most-significant bit PIO programmed I/O PPP point-to-point protocol MQFP metric quad-flat pack RAM random-access ...
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Pin Information 3.1 Pin Diagram GND 1 DB[7] 2 DB[6] 3 DB[5] 4 DB[4] 5 DB[3] 6 DB[2] 7 DB[1] 8 DB[0] 9 GND DMAACK* 12 DMAREQ* 13 N/C 14 N/C 15 N/C 16 N/C ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Pin Compati- Names bility A_1284 SLCTIN* HstBsy AUTOFD* HstClk STROBE* nInit INIT* AkDaR PError q PerBsy BUSY PerClk ACK* nDatAv FAULT* XFlag SELECT 3.2 Pin List The following naming conventions are used in the ...
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Pin Name Type DB[15:0] I/O DS* I DTACK* AR OUTEN I RESET* I R/W* I DMAREQ* O DMAACK* I SVCREQP* OD SVCACKP* I DGRANT* I DPASS* O PD[7:0] I/O GP[7:0] I/O A_1284 I nInit I HstBsy I HstClk I PerBsy ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 3.3 Pin Descriptions Symbol Pin No. Type A[6:0] 84–90 I BYTESWAP 82 I CLK 73 I CLK CS DB[15:0] 92–99, 2–9 I/O DS DTACK OUTEN 83 ...
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Symbol Pin No. Type SVCREQP SVCACKP DGRANT DPASS PD[7:0] 41–48 I/O GP[7:0] 53–60 I/O A_1284 31 I nInit 34 I HstBsy 32 I HstClk 33 I NOTE: The above four parallel handshake ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Symbol Pin No. Type NOTE: The above five parallel handshake signals are driven by the slave in an IEEE Std 1284 interface, and as such are outputs from the CD1283. Their functions depend on ...
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Register Summary Local CPU communication with the CD1283 occurs through a register set. Within this register set, there are four types of registers: • Global, common to all functions of the device • Parallel pipeline • Parallel port • ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Table 2. Virtual Registers Name Hex Bit 7 Bit 6 † EOSRR 60 X PIVR 40 X † ‘X’ indicates ‘don’t care’. Table 3. Parallel Pipeline Registers Name Hex Bit 7 Bit 6 DER ...
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Table 4. Parallel Port Registers (Sheet Name Hex Bit 7 Bit 6 ODR OVR 2B PerBsy PerClk PCIER PCISR PCR 20 ManMd E1284 SCR SPR ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 5.0 Functional Description 5.1 Device Architecture The CD1283 consists of dedicated logic tailored to the function of sending and receiving parallel data. The device implements an IEEE 1284-compliant parallel port with a specialized data ...
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Figure 2. Functional Block Diagram BUS INTERFACE AND DMA LOGIC Figure 3. Internal Address Generation CPU ADDRESS AER The CD1283 is a synchronous device. All internal operations occur on edges and levels (phases) of the internal clock. The internal clock ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 5.2.1 Read Cycles Read cycles are initiated when both the CS* and DS* inputs are activated and the R/W* (read/ write) input is high. All strobes and address inputs must meet the setup times ...
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FIFO has less than 2 bytes remaining (reverse direction). In the forward direction, the DMA controller logic responds by placing data on the 16-bit data bus and driving the DMAACK* input low. This cycle is repeated until the FIFO has ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Section 5.2.4). However, the software can easily change this by clearing the DMAen bit (PFCR[6]) at the start of the interrupt service routine and setting it again at the end SVCREQP* and ...
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As previously mentioned, the upper 5 bits of the LIVR reflect what the CPU loaded into them during initialization of the CD1283s. These bits are used as a unique chip identification number. Now the CPU can determine which CD1283 responded ...
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CD1283 — IEEE 1284-Compatible Parallel Interface • IDReq for slave ID requests from the remote master. • nINIT for initialization pulses from the master (Compatibility mode only) Any or all of these bits may be set, based on the mode ...
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Figure 5. Interrupt Generation Logic (Continued) A1284 signal transition nInit signal transition from low-to-high, and from low-to-high, and A1284(ODR[3 nInit(ODR[2 A1284 signal transi- nInit signal transition tion from high-to-low, from high to low, and and nInit(ZDR[2]) ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Figure 5. Interrupt Generation Logic (Continued) DMAwrerr (DER[7]) DMArderr (DER[6]) (DMAACK* w/o (DMAACK* w/o DMAREQ*) DMAREQ*) HR1wrerr (DER[3]) HR1rderr (DER[2]) (write to non-empty (Read from empty HR1) HR1)) DataErr OneChar Timeout (PFSR[0]) (PFSR[1]) (PFSR[5]) ...
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Figure 6. Control Signal Generation ADDRESS CPU DECODE ADDRESS LOGIC CPU I/O CONTROL A direction change (DirCh) interrupt occurs when the remote master has reversed the interface from ECP forward to ECP reverse or ECP reverse to ECP forward. The ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 5.3.1 Hardware-Activated Acknowledge When conditions within the parallel channel require attention, a request is made through the SVCREQP* output. If the system is interrupt driven, this output is connected to the CPU interrupt- generation ...
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Centronics -compatible mode. These modes include Compatibility mode, Reverse-Nibble mode, Reverse-Byte mode, ECP (Extended Capabilities port) with and without RLE (run-length encoding, and the EPP (Enhanced Parallel port). The IEEE 1284-compliant parallel port consists of two major ...
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CD1283 — IEEE 1284-Compatible Parallel Interface In the receive direction, the DMA request is removed when there are not at least two more bytes available to transfer or a tagged byte has moved into the data pipeline. In the latter ...
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Receiving Compressed Data RLE compressed data sequences that consist of a tagged RLE count followed by the compressed data character, are stored in the FIFO in compressed form. As data is moved from the FIFO into the data pipeline, ...
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CD1283 — IEEE 1284-Compatible Parallel Interface ‘0’. When Stale becomes ‘1’, the timeout is triggered, but not set until any DMA transfer is complete, the FIFO is empty, and there is no more than one character left in the pipeline. ...
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Signal Names The IEEE-1284 specification uses different names for the nine control signals, depending on the current mode of operation The names were selected to represent the most commonly used names amongst the various protocols. The CD1283 device operates ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 5.5.6 Manual Mode Manual mode allows direct control of the five output control signals and the PD bus not intended for data transfers, but rather for advanced diagnostics. Enter Manual mode by ...
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Parallel Port Interface to the FIFO The DMAdir bit indicates the current direction (0 the DMA logic. Due to a recent negotiation, this can differ from the current parallel-port interface direction. The CPU must change the direction after it ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 5.5.10 Data Transfers In Compatibility mode, incoming HstClk (STROBE*) pulses activate PerBsy (BUSY), and the data on PD[7:0] is held in latches. PerBsy protects the data latches by signalling the master it is not ...
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There is no mechanism in Compatibility mode for the slave to indicate that data is available for reverse transfers. The master must poll the slave by negotiating into a reverse mode and examining the nDatAv signal. The RevRq (SCR[0]) instructs ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Table 7. System Clock Setup CLK Freq. Time/Tic (MHz 5.8 General-Purpose I/O Port The CD1283 provides an 8-bit general-purpose port (GP[7:0]) used to control or give status of external functions. Each ...
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Figure 10. Cable Connection CD1283 BIDIRECTIONAL SIGNAL LINE OUTPUT SIGNAL LINE INPUT SIGNAL LINE Caution: Transient protection is not implemented inside the CD1283 device, therefore transient voltages may cause damage. Laboratory testing has shown that this type of protection is ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Figure 11. External Buffer Control TO CD1283 PDBEN EBDIR 5.10 Hardware Configurations The simplicity of the CPU interface to the CD1283 allows the device to be designed into systems that employ popular microprocessors such ...
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Interfacing to an Intel Microprocessor-Based System With very little additional logic, the CD1283 can interface to any system based on a processor in the Intel 80x86 family. 80286-based system. To provide the proper strobes and controls, the IOR* and ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 5.10.2 Interfacing to a Motorola Microprocessor-Based System Interfacing to a Motorola 68000 family device is relatively simple. Bus timing and interface signal definitions closely match those of the 68000 microprocessor, which allows a direct ...
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Programming 6.1 Overview As shown in the register summary tables large array of registers. These registers control all aspects of device behavior. Most registers are only modified once, during initialization, and rarely modified during normal operation. ...
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CD1283 — IEEE 1284-Compatible Parallel Interface useful in slow systems that cannot guarantee that the CPU can check the register after it is cleared or before it is loaded with the revision code. This procedure is also used as part ...
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The following section of programming code shows a typical initialization sequence preparing the parallel channel for Compatibility mode data reception and enabling negotiation into all modes, except EPP. This procedure can also be used as part of a diagnostic test ...
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CD1283 — IEEE 1284-Compatible Parallel Interface When the SVCACK* is activated, the SVCREQP* is deactivated. If the SVCACKP* signal is not activated, then the service request must be removed by clearing PpIreq (PIR[7]), and the source of the interrupt must ...
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Figure 16. Polling Flow Chart POLL DEVICE AGAIN DMAREQ SET SERVICE DMA REQUEST DirCh CHANGE DIRECTION RETURN ID TO HOST RESET PRINTER 6.3 ASCII Code Tables Table 8. Hexadecimal — Character (Sheet NUL 01 SOH 02 ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Table 8. Hexadecimal — Character (Sheet ...
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Detailed Register Descriptions This section presents a detailed description of each register. Registers have two formats: full eight bits, where the entire content defines a single function; or the register is a collection of bits, grouped singly or in ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 7.1.3 General-Purpose I/O Direction Register Register Name: GPDIR Register Description: General-Purpose I/O Direction Access: R/W Bit 7 Bit 6 Bit 5 Dir7 Dir6 Dir5 7.1.4 General-Purpose I/O Register Register Name: GPIO Register Description: General-Purpose ...
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Bit PPireq: Internal logic sets this bit to generate the external service request output direct reflection of the inverse state of the SVCREQP* pin the active-high output of the latch that drives the SVCREQP* 7 ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 7.2 Virtual Registers The CD1283 has two operational contexts: a normal context that allows host access to most registers and any channel, and a service-acknowledge context, allowing host access to some registers specific to ...
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Table 10. PIVR[2:0] Encoding IT2 IT1 0 0 • • 7.3 Parallel Pipeline Registers 7.3.1 Data Error Register Register Name: DER Register Description: Data Error Access: Read only Bit 7 ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 7.3.2 DMA Buffer Data Register Register Name: DMABUF Register Description: DMA Buffer Data high Access: R/W Bit 15 Bit 14 Bit 13 Register Name: DMABUF Register Description: DMA Buffer Data low Access: R/W Bit ...
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Bit HR1full and HR1tag:These two bits indicate status of PFHR1. Bit 7 indicates that the register contains data and 7:6 bit 6 indicates that the data is tagged. Both bits can be set simultaneously. HR2full and HR2tag:These two bits ...
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CD1283 — IEEE 1284-Compatible Parallel Interface The computed value is rounded up to the next largest whole hex value, in this case ‘0x3000’. Load HTVR with the most-significant 8 bits of this value, left-shifted two places since HTVR is a ...
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Parallel Auxiliary Control Register Register Name: PACR Register Description: Parallel Auxiliary Control Access: R/W Bit 7 Bit 6 Bit 5 ShrtTen ShrtStal StaleOff The PACR provides some special functions for the parallel data path and interrupt-generation circuitry. The upper ...
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CD1283 — IEEE 1284-Compatible Parallel Interface This register can be used to issue a hardware reset to the parallel channel . Bit 7:1 These bits are not used and must always be ‘0’. PChReset: When this bit is set, it ...
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Bit Set Tag: This bit specifies that the next character written to the parallel channel through the PFHR1 tagged ECP or EPP special character. This bit is cleared by the write to PFHR1, thus ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Register Name: PFHR2 Register Description: Parallel FIFO Holding Register 2 Access: R/W Bit 7 Bit 6 Bit 5 These two 1-byte registers provide a data pipeline between the FIFO and DMA buffer. Data always ...
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The PFSR is read-only and provides current FIFO and data pipeline status. Host software should examine these bits in response to pipeline interrupts or for polling operations. This register is not directly cleared by reset, but the individual bits will ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 7.3.15 Run-Length Count Register Register Name: RLCR Register Description: Run-Length Count Access: R/W Bit 7 Bit 6 Bit 5 0 This register works with PFHR1 and PFHR2 to perform run-length encoding/decoding when the RLEen ...
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Stale Data Timer Period Register Register Name: SDTPR Register Description: Stale Data Timer Period Access: R/W Bit 7 Bit 6 Bit 5 This register provides a user-defined period value for use as the timeout value of the stale data ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Bit 7:4 These read-only bits are always ‘0’. 3 A1284 2 nInit: (active-low Init input) 1 HstBsy: (Host Busy) 0 HstClk: (Host Clock) 7.4.3 Manual Data Register Register Name: MDR Register Description: Manual Data ...
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Negotiation Status Register NSR Negotiation Status R NegOK NegFl HostTO The results of negotiation attempts are stored in this register. Bit 7 NegOK: The state of this bit indicates that the negotiation was successful. Negotiation Failed: ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Any change in the mode of the parallel port is reported to the peripheral host by interrupt if the NegCh bit is set in the PCIER; host software then reads the NSR to determine ...
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Parallel Channel Interrupt Enable Register Register Name: PCIER Register Description: Parallel Channel Interrupt Enable Access: R/W Bit 7 Bit 6 Bit 5 0 TimEn NegCh 7.4.9 Parallel Channel Interrupt Status Register Register Name: PCISR Register Description: Parallel Channel Interrupt ...
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CD1283 — IEEE 1284-Compatible Parallel Interface This register controls the overall configuration of the parallel port, each of which is described in IEEE 1284 format below. Bit 7:5 Mode Control: These three bits control the type of transfer desired and ...
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This register allows the peripheral host processor to issue special commands to the channel control state-machine. In response, the state-machine will perform the indicated IEEE STD 1284-defined handshake on the parallel interface. Bit 7:5 These read-only bits are always ‘0’. ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Table 11. SPR Binary Values to Set 500-ns Pulse Widths Clock SPR Value (MHz 7.4.13 Signal Status Register Register Name: SSR Register Description: Signal Status Access: R/W Bit 7 Bit 6 ...
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This special-purpose register allows the local CPU to issue a hard reset of the device through software. The RCR performs the same function as the CCR in the CD1283, except that the only command available is the reset command. To ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 8.0 Electrical Specifications Caution: Before beginning any new design with this device, please contact Intel for the latest errata information. This datasheet is in reference to Revision E or newer devices. 8.1 Absolute Maximum ...
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I Data bus tristate leakage current LL I Open-drain output leakage current OC I Power supply current CC C Input capacitance IN C Output capacitance OUT NOTES 2.7 V minimum on RESET* and CLK ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 8.3 AC Characteristics 8.3.1 Asynchronous Timing Refer to Figure 17 through (@ V Table 12. Asynchronous Timing Reference Parameters (Sheet Timing Figure No RESET* low pulse width 1 ...
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Table 12. Asynchronous Timing Reference Parameters (Sheet Timing Figure No. The following timing numbers are for the back-to-back asynchronous DMA timing diagrams Hold time, DMAACK* active (DMA read/write Delay, data valid after ...
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CD1283 — IEEE 1284-Compatible Parallel Interface . Figure 18. Clock Timing CLK Figure 19. Asynchronous Read Cycle Timing t 2 A[6: R/W* CS* DS* DB[15:0] DTACK ...
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Figure 20. Asynchronous Write Cycle Timing t 2 A[6: R/W* CS* DS* DB[15:0] DTACK* Datasheet IEEE 1284-Compatible Parallel Interface — CD1283 ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Figure 21. Asynchronous Service Acknowledge Cycle Timing t 2 A[6: R/W* SVCACK* SVCREQ DS* DGRANT* DB[15:0] DTACK* DPASS ...
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Figure 22. Asynchronous DMA Read Cycle Timing CLK DMAACK* DMAREQ* DB[15:0] NOTES: 1. The DMA handshake operates in asynchronous mode only if the AsyncDMA bit is set in PACR DMAACK* is released after point ‘a,’ but before point ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Figure 24. Asynchronous DMA Write Cycle Timing CLK DMAACK* DMAREQ* DB[15:0] NOTE: This Figure 24 is still valid, however, Figure 25. Asynchronous DMA Write Cycle Timing CLK DMAACK* SYNCHRONIZED DMAREQ* DMAACK* DB[15:0] NOTE: The ...
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Table 13. Synchronous Timing Reference Parameters Timing Figure Number t 26 Setup time, CS* and DS rising edge Setup time, R/ rising edge Setup time, address valid to C1 rising ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Figure 26. Synchronous Read Cycle Timing CLK t 1 DS A[6:0] DB[15:0] DTACK ...
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Figure 27. Synchronous Write Cycle Timing CLK t 1 DS A[6:0] DB[15:0] DTACK* Datasheet IEEE 1284-Compatible Parallel Interface — CD1283 ...
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CD1283 — IEEE 1284-Compatible Parallel Interface Figure 28. Synchronous Service Acknowledge Cycle Timing CLK t 12 SVCACKP* SVCREQ* DPASS DS*, DGRANT R/W* DB[15:0] DTACK ...
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Figure 29. Synchronous DMA Write Cycle Timing (Two Back-to-Back 3-Cycle DMA Writes CLK t 15 DMAREQ DMAACK* DB[15:0] NOTE: The data is sampled on the second rising edge of CLK following the assertion of DMAACK*, as ...
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CD1283 — IEEE 1284-Compatible Parallel Interface 9.0 Package Dimensions 13.90 (0.547) 14.10 (0.555) Pin 1 Indicator Pin 100 Pin 1 0.65 (0.026) 0.95 (0.037) 0.13 (0.005) 0.23 (0.009) 3.40 (0.134) MAX NOTES: 1. Dimensions are in millimeters (inches), and controlling ...
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... The order number for the CD1283 is: Product line: Communications, Data Part number Internal reference number † Contact Intel Corporation for up-to-date information on revisions. Datasheet IEEE 1284-Compatible Parallel Interface — CD1283 SCD128310QCE Temperature range Commercial Package type: MQFP (metric quad flat pack) † Revision 91 ...
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Index A abbreviations 11 absolute maximum ratings 76 AC characteristics 78 acronyms 11 ASCII code tables decimal 52 hexadecimal 51 B bus interface 33 BYTESWAP 34 C cable connection 43 Compatibility mode status 40 context 32 context switch hardware-activated 32 ...
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DirCh 31 EPPAW 28 IDReq 31 NegCh 28 invalid termination 39 IVR 38 M modes ECP 34 EPP 38 Manual 38 Reverse Byte 40 Reverse Nibble 40 O odd-byte transfers 25 ODR 38 ...
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OVR 21, 70 PCIER 21, 71 PCISR 21, 71 PCR 21, 71 SCR 21, 39, 72 SPR 21, 73 SSR 21, 74 ZDR 21, 74 Virtual EOSRR 20 PIVR 20, 56 reset, device 47 RLE (run-length-encoding sample system ...