PEEL18CV8Z ANACHIP [Anachip Corp], PEEL18CV8Z Datasheet

PEEL18CV8Z

Manufacturer Part Number

PEEL18CV8Z

Description

CMOS Programmable Electrically Erasable Logic Device

Manufacturer

ANACHIP [Anachip Corp]

Datasheet

1.PEEL18CV8Z.pdf (10 pages)

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This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under

any patent accompany the sale of the product.

Features

General Description

The PEEL™18CV8Z is a Programmable Electrically Erasable

Logic (PEEL™) SPLD (Simple Programmable Logic Device)

that features ultra-low, automatic “zero” power-down operation.

The “zero power” (100 µA max. Icc) power-down mode makes the

PEEL™18CV8Z ideal for a broad range of battery-powered

portable equipment applications, from hand-held meters to PCM-

CIA modems. EE-reprogrammability provides both the conve-

nience of fast reprogramming for product development and quick

product personalization in manufacturing, including Engineering

Change Orders.

Figure 7 Pin Configuration

Ultra Low Power Operation

CMOS Electrically Erasable Technology

Application Versatility

- Vcc = 5 Volts ±10%

- Icc = 10 µA (typical) at standby

- Icc = 2 mA (typical) at 1 MHz

- Superior factory testing

DIP

PLCC

Reprogrammable in plastic package

Reduces retrofit and development costs

Replaces random logic

Super set of standard PLDs

Pin and JEDEC compatible with 16V8

Ideal for use in power-sensitive systems

CMOS Programmable Electrically Erasable Logic Device

I/CLK

TSSOP

™

GND

SOIC

PEEL™ 18CV8Z -25

VCC

I/O

1/10

The PEEL™18CV8Z is logically and functionally similar to

Anachip’s 5 Volt PEEL™18CV8 and 3 Volt PEEL™18LV8Z.

The

PEEL™18CV8 include the addition of programmable clock

polarity, a product term clock, and variable width product terms in

the AND/OR Logic Array.

Like the PEEL™18CV8, the PEEL™18CV8Z is logical superset

of the industry standard PAL16V8 SPLD. The PEEL™18CV8Z

provides additional architectural features that allow more logic to

be incorporated into the design. Anachip’s JEDEC file translator

allows easy conversion of existing 20 pin PLD designs to the

PEEL™18CV8Z architecture without the need for redesign. The

PEEL™18CV8Z architecture allows it to replace over twenty

standard 20-pin DIP, SOIC, TSSOP and PLCC packages.

Figure 8 Block Diagram

Architectural Flexibility

Programmable clock; pin 1 or p-term

Programmable clock polarity

Enhanced architecture fits in more logic

113 product terms x 36 input AND array

10 inputs and 8 I/O pins

12 possible macrocell configurations

Asynchronous clear, Synchronous preset

Independent output enables

20 Pin DIP/SOIC/TSSOP and PLCC

differences

CLK MUX (Optional)

between

the

PEEL™18CV8Z

Rev. 1.0 Dec 16, 2004

and

Related parts for PEEL18CV8Z

PEEL18CV8Z Summary of contents

Page 1

CMOS Programmable Electrically Erasable Logic Device Features Ultra Low Power Operation - Vcc = 5 Volts ±10% - Icc = 10 µA (typical) at standby - Icc = 2 mA (typical MHz CMOS Electrically Erasable Technology - Superior ...

Page 2

Anachip Corp. www.anachip.com.tw 2/10 Rev. 1.0 Dec 16, 2004 ...

Page 3

Function Description The PEEL™18CV8Z implements logic functions as sum-of- products expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further ...

Page 4

I/O pin. Otherwise, the output buffer is switched into the high-impedance state. Under the control of the output enable term, the I/O pin can func- tion as a dedicated input, a dedicated output bi-directional I/ O. Opening ...

Page 5

Configuration # ...

Page 6

Design Security The PEEL™18CV8Z provides a special EEPROM security bit that prevents unauthorized reading or copying of designs pro- grammed into the device. The security bit is set by the PLD pro- grammer, either at the conclusion of the programming ...

Page 7

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Voltage Applied to Any Pin Output Current O T Storage Temperature ST T Lead Temperature LT Operating Range Symbol Parameter V Supply Voltage CC T ...

Page 8

Symbol 5 t Input to non-registered output Input to output enable Input to output disable OD t Clock to Output CO1 t Clock to comb. output delay via internal registered feedback CO2 t Clock ...

Page 9

... PEEL™ Device and Array Test Loads Technology CMOS TTL Ordering Information Part Number PEEL18CV8ZP-25 (L) PEEL18CV8ZJ-25 (L) PEEL18CV8ZS-25 (L) PEEL18CV8ZT-25 (L) PEEL18CV8ZPI-25 (L) PEEL18CV8ZJI-25 (L) PEEL18CV8ZSI-25 (L) PEEL18CV8ZTI-25 (L) Part Number Package P = 20-pin Plastic 300mil DIP J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC 20-pin SOIC 300 mil Gullwing T = 20-pin TSSOP 170mil Anachip Corp. www.anachip.com.tw ...

Page 10

Anachip Corp. Head Office, 2F, No. 24-2, Industry E. Rd. IV, Science-Based Industrial Park, Hsinchu, 300, Taiwan Tel: +886-3-5678234 Fax: +886-3-5678368 Email: sales_usa@anachip.com Website: http://www.anachip.com ©2004 Anachip Corp. Anachip reserves the right to make changes in specifications at any time ...

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