PEEL18LV8ZP-25L ANACHIP [Anachip Corp], PEEL18LV8ZP-25L Datasheet

PEEL18LV8ZP-25L

Manufacturer Part Number

PEEL18LV8ZP-25L

Description

CMOS Programmable Electrically Erasable Logic Device

Manufacturer

ANACHIP [Anachip Corp]

Datasheet

1.PEEL18LV8ZP-25L.pdf (10 pages)

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Features

•

General Description

The PEEL18LV8Z is a Programmable Electrically Erasable

Logic (PEEL) SPLD (Simple Programmable Logic Device)

that operates over the supply voltage range of 2.7V-3.6V

and features ultra-low, automatic "zero" power-down

operation. The PEEL18LV8Z is logically and functionally

similar to Anachip's 5V PEEL18CV8 and PEEL18CV8Z.

The "zero power" (25 µA max. Icc) power-down mode

makes the PEEL18LV8Z ideal for a broad range of battery-

powered portable equipment applications, from hand-held

meters

provides both the convenience of fast reprogramming for

product development and quick product personalization in

manufacturing, including Engineering Change Orders.

This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights

under any patent accompany the sale of the product.

Low Voltage, Ultra Low Power Operation

- Vcc = 2.7 to 3.6 V

- Icc = 5 µA (typical) at standby

- Icc = 1.5 mA (typical) at 1 MHz

- Meets JEDEC LV Interface Spec (JEDSD8-A)

- 5 Volts tolerant inputs and I/O’s

CMOS Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

Application Versatility

- Replaces random logic

- Super set of standard PLDs

- Pin and JEDEC compatible with 16V8

- Ideal for battery powered systems

- Replaces expensive oscillators

I/CLK1

DIP

GND

PLCC-J

PCMCIA

Figure 1 - Pin Configuration

9 10 11 12 13

modems.

I/O

CMOS Programmable Electrically Erasable Logic Device

I/CLK1

GND

EE-reprogrammability

PEEL™ 18LV8Z-25 / I-35

TSSOP

I/O

SOIC

I/O

1/10

The

PEEL18CV8 include the addition of programmable clock

polarity, p-term clock, and Schmitt trigger input buffers on

all inputs, including the clock. Schmitt trigger inputs allow

direct input of slow or noisy signals.

Like the PEEL18CV8, the PEEL18LV8Z is a logical

superset of the industry standard PAL16V8 SPLD. The

PEEL18LV8Z provides additional architectural features that

allow more logic to be incorporated into the design.

Anachip's JEDEC file translator allows easy conversion of

existing 20 pin PLD designs to the PEEL18LV8Z

architecture

PEEL18LV8Z architecture allows it to replace over twenty

standard 20-pin DIP, SOIC, TSSOP and PLCC packages.

•

Architectural Flexibility

- Enhanced architecture fits in more logic

- 113 product terms x 36 input AND array

- 10 inputs and 8 I/O pins

- 12 possible macrocell configurations

- Asynchronous clear, Synchronous preset

- Independent output enables

- Programmable clock; pin 1 or p-term

- Programmable clock polarity

- 20 Pin DIP/SOIC/TSSOP and PLCC

- Schmitt triggers on clock and data inputs

Schmitt Trigger Inputs

- Eliminates external Schmitt trigger devices

- Ideal for encoder designs

differences

without

C LK MU X (Optional)

Figure 2 - Block Diagram

between

the

need

the

for

PEEL18LV8Z

Rev. 1.0 Dec 16, 2004

redesign.

The

and

Related parts for PEEL18LV8ZP-25L

PEEL18LV8ZP-25L Summary of contents

Page 1

CMOS Programmable Electrically Erasable Logic Device Features • Low Voltage, Ultra Low Power Operation - Vcc = 2 Icc = 5 µA (typical) at standby - Icc = 1.5 mA (typical MHz - Meets ...

Page 2

Schm itt Trigger Inputs Anachip Corp. www.anachip.com. tio Figure 3 - PEEL18LV8Z Logic Array Diagram 2/10 I* Rev. 1.0 Dec 16, 2004 ...

Page 3

Function Description The PEEL18LV8Z implements logic functions as sum-of- products expressions in a programmable-AND/fixed-OR logic array. Programming the connections of input signals into the array creates user-defined functions. User- configurable output structures in the form of I/O macrocells further increase ...

Page 4

Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset. Output Polarity Each macrocell can be configured to implement active-high or active-low logic. Programmable polarity eliminates the ...

Page 5

As a result of the "Zero-Power" feature, significant power savings can be realized for combinatorial or ...

Page 6

ICC 0.1 0.01 0.01 0.1 1 Frequency in MHz Figure 6 - Typical ICC vs. Input Clock Frequency for the 18LV8Z Design Security The PEEL18LV8Z provides a special EEPROM security bit that prevents unauthorized reading ...

Page 7

Table 1 - Absolute Maximum Ratings Symbol Parameter V Supply Voltage Voltage Applied to Any Pin I Output Current O T Storage Temperature ST T Lead Temperature LT Table 2 - Operating Range Symbol ...

Page 8

Table 4 - A.C. Electrical Characteristics 9 Over the operating range Symbol Parameter 6 tPD Input to non-registered output in continuous mode 6 7 tOE Input to output enable 6 7 tOD Input to output disable tCO1 Clock to Output ...

Page 9

... Standard Load Output Technology CMOS TTL Ordering Information Part Number PEEL18LV8ZP-25 (L) PEEL18LV8ZPI-35 (L) PEEL18LV8ZJ-25 (L) PEEL18LV8ZJI-35 (L) PEEL18LV8ZS-25 (L) PEEL18LV8ZSI-35 (L) PEEL18LV8ZT-25 (L) PEEL18LV8ZTI-35 (L) Part Number Package P = 20-pin Plastic 300 mil DIP J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC 20-pin SOIC 300 mil Gullwing T = 20-pin TSSOP 170mil Anachip Corp. ...

Page 10

Anachip Corp. Head Office 2F, No. 24-2, Industry E. Rd. IV, Science-Based Industrial Park, Hsinchu, 300, Taiwan Tel: +886-3-5678234 Fax: +886-3-5678368 Email: sales_usa@anachip.com Website: http://www.anachip.com ©2004 Anachip Corporation Anachip reserves the right to make changes in specifications at any time ...

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