54FCT377 NSC [National Semiconductor], 54FCT377 Datasheet

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54FCT377

Manufacturer Part Number
54FCT377
Description
Octal D-Type Flip-Flop with Clock Enable
Manufacturer
NSC [National Semiconductor]
Datasheet

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© 1999 National Semiconductor Corporation
54FCT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ’FCT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Ordering Code
Connection Diagram
TRI-STATE
54FCT377DMQB
54FCT377FMQB
54FCT377LMQB
®
is a registered trademark of National Semiconductor Corporation.
Military
Pin Assignment for
DIP and Cerpack
DS100952-1
DS100952
J20A
W20A
E20A
Package
Number
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Features
n Clock enable for address and data synchronization
n Eight edge-triggered D flip-flops
n Buffered common clock
n See ’FCT273 for master reset version
n See ’FCT373 for transparent latch version
n See ’FCT374 for TRI-STATE
n TTL input and output level compatible
n CMOS power consumption
n Output sink capability of 32 mA, source capability of
n Standard Microcircuit Drawing (SMD) 5962-8762701
Names
D
CE
CP
Q
applications
12 mA
Pin
0
0
–D
–Q
7
7
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
Pin Assignment for LCC
Package Description
Description
®
version
DS100952-11
October 1999
www.national.com

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54FCT377 Summary of contents

Page 1

... The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Ordering Code Military 54FCT377DMQB J20A 54FCT377FMQB W20A 54FCT377LMQB E20A Connection Diagram Pin Assignment for DIP and Cerpack DS100952-1 TRI-STATE ® registered trademark of National Semiconductor Corporation. ...

Page 2

Truth Table Operating Mode Load “1” Load “0” Hold (Do Nothing HIGH Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition L = LOW Voltage Level I = LOW Voltage Level ...

Page 3

Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic V Pin Potential to CC Ground Pin Input ...

Page 4

AC Electrical Characteristics Symbol Parameter t Propagation Delay PLH PHL n AC Operating Requirements Symbol Parameter t (H) Setup Time, HIGH s t (L) or LOW (H) Hold Time, HIGH ...

Page 5

AC Loading DS100952-4 *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load = 1.5V FIGURE Input Pulse Requirements Amplitude Rep. Rate 3.0V 1 MHz 500 ns 2.5 ns FIGURE 3. Test Input ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted www.national.com 20-Lead Ceramic Chip Carrier NS Package Number E20A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Dual-In-Line Package NS Package Number J20A 20-Lead Ceramic Flatpack NS Package Number W20A 7 www.national.com ...

Page 8

LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support ...

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