ATSHA204 ATMEL [ATMEL Corporation], ATSHA204 Datasheet - Page 25

• Manufacturer Part Number: ATSHA204
• Description: Atmel CryptoAuthentication
• Manufacturer: ATMEL [ATMEL Corporation]

6.5
6.6
I
When the ATSHA204 is awake and not busy, the bus master can retrieve the current buffer contents from the device using an
I
has been run (See Section 8. “Commands”), otherwise the size of the block (and the first byte returned) will always be four:
count, status/error, and 2-byte CRC. The bus timing is shown in Figure 7-3 in Section 7.3.2.
Table 6-3.
The status, error, or command outputs can be read repeatedly by the master. Each time a read command is sent to the
ATSHA204 along the I
for details on how the device handles the address counter.
If the ATSHA204 is busy, idle, or asleep, it will NACK the device address on a read sequence. If a partial command has been
sent to the device, then it will NACK the device address, but float the bus during the data intervals.
Address Counter
Writes to and/or reads from the ATSHA204 I/O buffer over the I
I
the operation of the device.
The first byte transmitted to the device is treated as the size byte. Any attempt to send more than this number of bytes or any
attempts to write beyond the end of the I/O buffer (84 bytes) will cause the ATSHA204 to NACK those bytes.
After the host writes a single command byte to the input buffer, reads from the host are prohibited until after the device
completes command execution. Attempts to read from the device prior to the last command byte being sent will result in an
ACK of the device address but all ones (0xFF) on the bus. If the master attempts to send a read byte to the device during
command execution, the device will NACK the device address.
Data may be read from the device under the following three conditions:
Any attempt to read beyond the end of the valid output buffer returns 0xFF to the system – the address counter does not wrap
around to the beginning of the buffer.
There may be situations where the system may wish to re-read the output buffer; for example, when the CRC check reveals
an error. In this case, the master should send a two-byte sequence to the ATSHA204 consisting of the correct device address
and a word address of 0x00 (Reset, per Table 6-2), followed by a stop condition. This causes the address counter to be reset
to zero, and permits the data to be re-written (re-read) to (from) the device. This address reset sequence does not prohibit
subsequent read operations if data was available for reading in the I/O buffer prior to the sequence execution.
After one or more read operations to retrieve the results of a command execution, the first write operation resets the address
counter to the beginning of the I/O buffer.
2
2
2
Atmel ATSHA204
Device Address
Data
C read. If valid command results are available, the size of the block returned is determined by the particular command that
C byte or block write/read protocols can be used. The number of bytes transferred with each block sequence does not affect
C Transmission from the Atmel ATSHA204 Device
•
•
•
On power up, the single byte, 0x11 (See Section 8.1.3), can be read inside a four byte block.
If a complete block has been received by the device, but there are any errors in parsing or executing the command,
Upon completion of command execution, from 1-32 bytes of command result are available to be read inside a block
a single byte of error code is available, also inside a four byte block.
of 4-35 bytes.
I
2
C transmission from Atmel ATSHA204
I
Device Address
Data
2
C Name
2
C interface, the device transmits the next sequential byte in the output buffer. See the following section
1,N
Direction
To slave
To master
Description
This byte selects a particular device on the I
ATSHA204 will be selected if bits 1-7 of this byte match bits 1-7 of the
I2C_Address byte in the configuration zone. Bit 0 of this byte is the
standard I
following the device address travel from the slave to the master (read).
The output block, consisting of the count and status/error byte or the
output packet followed by the two-byte CRC per Section 8.1.
2
2
C interface are treated as if the device were a FIFO. Either the
C R/W pin, and should be one to indicate that the bytes
Atmel ATSHA204 [DATASHEET]
2
C interface, and the Atmel
8740D−CRYPTO−3/12
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