W6694CD WINBOND [Winbond], W6694CD Datasheet

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W6694CD

Manufacturer Part Number
W6694CD
Description
USB Bus ISDN S/T-Controller
Manufacturer
WINBOND [Winbond]
Datasheet
Preliminary W6694
PASSIVE USB-ISDN S/T-CONTROLLER
W6694
USB Bus ISDN S/T-Controller
Data Sheet
The information described in this document is the exclusive intellectual property of Winbond
Electronics Corp and shall not be reproduced without permission from Winbond.
Winbond is providing this document only for reference purposes for W6694-based system design.
Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to
change without notice.
Publication Release Date: October 2000
- 1 -
Revision A1

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W6694CD Summary of contents

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PASSIVE USB-ISDN S/T-CONTROLLER USB Bus ISDN S/T-Controller The information described in this document is the exclusive intellectual property of Winbond Electronics Corp and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes ...

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Table of Contents- 1. GENERAL DESCRIPTION ............................................................................................................ 4 2. FEATURES ................................................................................................................................... 4 ISDN .............................................................................................................................................. 4 USB ............................................................................................................................................... 4 Other Features............................................................................................................................... 4 3. PIN CONFIGURATION.................................................................................................................. 5 4. PIN DESCRIPTION ....................................................................................................................... 6 5. SYSTEM DIAGRAM AND APPLICATIONS................................................................................... 8 6. BLOCK DIAGRAM ........................................................................................................................ ...

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Monitor Channel Transmit Register MOX Read/Write Address 09h ........................... 24 8.4 Programmable IO Registers ................................................................................................... 24 8.4.1 PIO Input Enable Register 8.4.2 PIO Output Register 1 8.4.3 PIO Output Register 2 8.4.4 PIO Data Register 8.5 B Channel Switch ...

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GENERAL DESCRIPTION The Winbond's single chip USB bus ISDN S/T interface controller W6694 is an all-in-one device suitable for ISDN Internet access. The integrated USB and ISDN design provides low cost, pure passive solution for USB-IDSN application. W6694 also ...

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PIN CONFIGURATION VDDU VDD3 UCLK1 41 UCLK2 42 VDD3I 43 VSS1 44 SR1 45 SR2 46 47 VDD1 48 SX1 ...

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PIN DESCRIPTION Table 4.1 W6694 Pin Descriptions SYMBOL PIN NO UCLK1 41 UCLK2 42 SR1 45 SR2 46 SX1 48 SX2 1 XTAL1 2 XTAL2 3 GCIDCL 6 GCIFSC 7 GCIDD 8 GCIDU 9 PFCK1 ...

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Pin Description, continued SYMBOL PIN NO. EPCS 17 EPSK 18 EPDI 19 EPDO 20 V 1 23, ...

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SYSTEM DIAGRAM AND APPLICATIONS Typical applications include: § USB passive TA for data only service § USB passive TA with one data plus one voice VDD D1 R1 VDD 1N4148 10K RESETN CB1 + 1uF CB2 CB3 CB4 CB5 ...

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BLOCK DIAGRAM S/T Interface GCI GCI Bus Control PCM PCM Port Codec Control Interface 7. FUNCTIONAL DESCRIPTIONS 7.1 USB Descriptions TAble 7.1 W6694 all USB Endpoints END TYPE DIRECTION* POINT 0 Control IN/OUT 1 Bulk OUT 2 Bulk IN ...

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USB standard requests are supported by W6694, and W6694 will respond to requests according to USB specification revesion 1.1. These includes “CLEAR_FEATURE, GET_CONFIGURATION, GET_DESCRIPTOR, GET_INTERFACE, GET_STATUS, SET_ADDRESS, SET_CONFIGURATION, SET_DESCRIPTOR, SET_FEATURE, SET_INTERFACE”. The “SYNC_FRAME” request is not supported. 7.1.1 Control-IN Transactions ...

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Get Configuration Descriptor, continued OFFSET FIELD 0 bLength 1 bDescriptorType 2 bInterfaceNumber 3 bAlternateSetting 4 bNumEndpoints 5 bInterfaceClass 6 bInterfaceSubClass 7 bInterfaceProtocol 8 iInterface 0 bLength 1 bDescriptorType 2 bInterfaceNumber 3 bAlternateSetting 4 bNumEndpoints 5 bInterfaceClass 6 bInterfaceSubClass 7 ...

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Get Configuration Descriptor, continued OFFSET FIELD 0 bLength 1 bDescriptorType 2 bEndpointAddress 3 bmAttributes 4 wMaxPacketSize 6 bInterval 0 bLength 1 bDescriptorType 2 bEndpointAddress 3 bmAttributes 4 wMaxPacketSize 6 bInterval 0 bLength 1 bDescriptorType 2 bEndpointAddress 3 bmAttributes 4 ...

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Control-OUT Transactions (Endpoint 0) 7.1.2.1 Device Clear Feature, Remote Wake-up BmRequestType bRequest 00H CLEAR_FEATURE On received this request from host, W6694 will not detect the incoming ISDN broadcast message. 7.1.2.2 Device Set Feature, Remote Wake-up BmRequestType bRequest 00H SET_FEATURE ...

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Contents of address byte: Bit 7 6 0/1 0 Bit 7: 0/1 = Read/Write Bit 4-0: Address offset of register. The data byte is the write data (write operation) or 00h (read operation). 7.1.4 Bulk-IN Transaction (Endpoint 2) Bulk-IN endpoint ...

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XFIFO. The continuous FFh will later be transmitted to corresponding B channel of ISDN interface. This Isochronous-OUT packet error will be reported to host, by setting bit ISOE of Isochronous-IN packet channel FIFO will recognize and ...

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B1_DATA B1 Channel Data These are B1 channel data, the length is indicated by B_LEN. B2_DATA B2 Channel Data These are B2 channel data, the length is indicated by B_LEN. 7.1.7 Isochronous-IN Transaction (Endpoint 5) After power on or reset, ...

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XDOV Transmit Data Overflow The corresponding XFIFO has overflow condition. Data in XFIFO are overwritten by incoming USB data. For D and B channel, the XFIFO is reset and disabled for that channel. This bit is cleared when XFIFO is ...

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EEPROM Contents : Offse t (Byte REGISTER DESCRIPTIONS 8.1 Interrupt Registers These registers will be read by Interrupt-IN packet only, so the USB host will periodically receive these data. These registers can not be read by ...

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Note: If S/T layer 1 function is disabled and GCI bus is enabled ( GCR register), CIR register is used to receive layer 1 indication code from U transceiver. In this case, the supported indication codes are: ...

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Command Register 1 Value after reset: 00h Writing 1 to the following bits will activate each corresponding function. Writing 0 to these bits has no effect DXRST DRRST DXEN DXRST D Channel Transmitter Reset Setting this ...

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RLP Remote Loopback Setting this bit activates the remote loopback function. The received 2B channels from the S interface are looped to the transmitted 2B channels of S/T interface. The D channel is not looped in this loopback function. This ...

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Layer 1 Command/Indication Register CIX Value after reset: 0Fh CIX3-0 Layer 1 Command Code Value of the command code transmitted to layer 1. A read to this register returns the previous written value. ...

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TLP Test Loopback When set this bit both the GCIDU and GCIDD lines are internally connected together. The GCI mode loopback test function: GCIDU is internally connected with GCIDD, external input on GCIDD is ignored. GRLP GCI Mode Remote Loopback ...

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MR bit always 1. In addition, the MDR interrupt is blocked, except for the first byte of a packet (if MRIE = 1 internally controlled according to Monitor channel protocol. In addition, the MDR interrupt is enabled ...

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OMn_1-0 Output Mode of IO Pin 3...0). Setting corresponding bits drive output pin with different output mode. Possible modes are: 00: always LOW 01: 0.5 second HIGH/LOW cycle 10: 1 second HIGH/LOW cycle 11: always HIGH These ...

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Layer1 B2 Receiver Select Register Value after reset: 05h RS2-0 Receiver Select These bits select the source where layer 1 B2 channel will receive data from. Possible values are: 000 (0): receive from ...

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EPCM Enable PCM Transmit/Receive 0: Disable data transmit/receive to/from PCM port. The frame synchronization clock is held LOW. The bit synchronization clock is LOW if both PCM ports are disabled. 1: Enable data transmit/receive to/from PCM port. The frame synchronization ...

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Power Supply PARAMETER 5V Input Voltage 3.3V Regulator Output Analog Ground Digital Ground 9.3 DC Characteristics SSA PARAMETER SYM. MIN. Low ...

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Capacitances of ISDN Pins 5 0V SSA PARAMETER Output Capacitance Against V Input Capacitance Load Capacitance Recommended Oscillator Circuits C C Crystal specifications PARAMETER Frequency Frequency Calibration ...

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Preliminary Switching Characteristics 9.4.1 PCM Interface Timing PBCK (1.536MHz) PFCK1 PFCK2 PTXD Port Port 2 1 PRXD Port Port 1 2 Note 1: These drawings are not to scale. Note 2: The frequency of PBCK ...

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PARAMETER PARAMETER DESCRIPTIONS ta1 PBCK pulse high ta2 PBCK pulse low ta3 Frame clock asserted from PBCK ta4 PTXD data delay from PBCK ta5 Frame clock deasserted from PBCK ta6 PTXD hold time from PBCK ta7 PRXD setup time to ...

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... ORDERING INFORMATION PART NUMBER PACKAGE TYPE W6694CD 48-pin LQFP 11. PACKAGE INFORMATION 48L LQFP ( 1.4 mm footprint 2.0 mm SEATING PLANE PRODUCTION FLOW Commercial + Controlling dimension: Millimeters Dimension in inch Symbol Min. Nom. Max. Min. ...

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Winbond Electronics (H.K.) Ltd. Winbond Electronics (H.K.) Ltd. Headquarters Headquarters Unit 9-15, 22F, Millennium City, Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; No. 378 Kwun Tong Rd; ...

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