QL3025-3PF144I QuickLogic Corp, QL3025-3PF144I Datasheet
QL3025-3PF144I
Manufacturer Part Number
QL3025-3PF144I
Description
Manufacturer
QuickLogic Corp
Datasheet
1.QL3025-3PF144I.pdf
(49 pages)
Specifications of QL3025-3PF144I
Package
QFP
Date_code
03+
Device Highlights
High Performance & High Density
• Up to 60,000 usable PLD gates with up to
• 300 MHz 16-bit counters, 400 MHz datapaths
• 0.35 µm four-layer metal non-volatile CMOS
Easy to Use/Fast Development
Cycles
• 100% routable with 100% utilization and
• Variable-grain logic cells provide high
• Comprehensive design tools include high quality
Advanced I/O Capabilities
• Interfaces with 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V buses
• Full JTAG boundary scan
• I/O cells with individually controlled registered
Up to 316 I/O Pins
• Up to 308 bidirectional input/output pins,
• Up to eight high-drive input/distributed network
© 2005 QuickLogic Corporation
316 I/Os
process for smallest die sizes
complete pin-out stability
performance and 100% utilization
Verilog/VHDL synthesis
for -1/-2/-3/-4 speed grades
input path and output enables
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
pins
pASIC 3 FPGA Family Data Sheet
• • • • • •
Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High
Performance and High Density
Up to Eight Low-Skew Distributed
Networks
• Two array clock/control networks are available to
• Up to six global clock/control networks are
High Performance
• Input + logic cell + output total delays under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
the logic cell flip-flop; clock, set, and reset inputs
— each can be driven by an input-only pin
available to the logic cell; F1, clock, set, and reset
inputs and the data input, I/O register clock,
reset, and enable inputs as well as the output
enable control — each can be driven by an input-
only pin, I/O pin, any logic cell output, or I/O cell
feedback
Figure 1:
Up to 1,584
pASIC 3 Logic Cells
www.quicklogic.com
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