EDE5116AJSE-6E-E Elpida Memory, Inc., EDE5116AJSE-6E-E Datasheet

EDE5116AJSE-6E-E

Manufacturer Part Number

EDE5116AJSE-6E-E

Description

Manufacturer

Elpida Memory, Inc.

Datasheet

1.EDE5116AJSE-6E-E.pdf (77 pages)

Specifications of EDE5116AJSE-6E-E

Package

BGA

Date_code

08+

Current page: 1 of 77
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Specifications

Document No. E1043E40 (Ver. 4.0)

Date Published February 2008 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Density: 512M bits

Organization

Package

Power supply: VDD, VDDQ

Data rate: 800Mbps/667Mbps (max.)

1KB page size

2KB page size (EDE5116AJSE)

Four internal banks for concurrent operation

Interface: SSTL_18

Burst lengths (BL): 4, 8

Burst type (BT):

/CAS Latency (CL): 3, 4, 5, 6

Precharge: auto precharge option for each burst

access

Driver strength: normal/weak

Refresh: auto-refresh, self-refresh

Refresh cycles: 8192 cycles/64ms

Operating case temperature range

32M words

16M words

8M words

60-ball FBGA (EDE5104/08AJSE)

84-ball FBGA (EDE5116AJSE)

Lead-free (RoHS compliant)

Row address: A0 to A13

Column address: A0 to A9, A11 (EDE5104AJSE)

Row address: A0 to A12

Column address: A0 to A9

Sequential (4, 8)

Interleave (4, 8)

Average refresh period

7.8 s at 0 C

3.9 s at 85 C

TC = 0 C to +95 C

16 bits

4 bits

8 bits

A0 to A9 (EDE5108AJSE)

EDE5104AJSE (128M words 4 bits)

EDE5116AJSE (32M words 16 bits)

EDE5108AJSE (64M words 8 bits)

4 banks (EDE5104AJSE)

4 banks (EDE5108AJSE)

4 banks (EDE5116AJSE)

85 C

95 C

512M bits DDR2 SDRAM

1.8V

0.1V

DATA SHEET

Features

Double-data-rate architecture; two data transfers per

clock cycle

The high-speed data transfer is realized by the 4 bits

prefetch pipelined architecture

Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

Differential clock inputs (CK and /CK)

DLL aligns DQ and DQS transitions with CK

transitions

Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

Data mask (DM) for write data

Posted /CAS by programmable additive latency for

better command and data bus efficiency

Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

Programmable RDQS, /RDQS output for making

organization compatible to

/DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation

Elpida Memory, Inc. 2007-2008

4 organization

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