NT5TU32M16AG-37B Nanya Technology, NT5TU32M16AG-37B Datasheet

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NT5TU32M16AG-37B

Manufacturer Part Number
NT5TU32M16AG-37B
Description
Manufacturer
Nanya Technology
Datasheet

Specifications of NT5TU32M16AG-37B

Case
BGA
Date_code
2005+

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NT5TU64M8AE(Green)
NT5TU32M16AG(Green)
512Mb DDR2 SDRAM
Features
CAS Latency and Frequency
Description
The 512Mb Double-Data-Rate-2 (DDR2) DRAMs is a high-
speed CMOS Double Data Rate 2 SDRAM containing
536,870,912 bits. It is internally configured as a quad-bank
DRAM.
The 512Mb chip is organized as either 32Mbit x 4 I/O x 4
bank, 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank
device. These synchronous devices achieve high speed dou-
ble-data-rate transfer rates of up to 533 Mb/sec/pin for gen-
eral applications.
The chip is designed to comply with all key DDR2 DRAM key
features: (1) posted CAS with additive latency, (2) write
latency = read latency -1, (3) normal and weak strength data-
output driver, (4) variable data-output impedance adjustment
and (5) an ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS pair in a source synchronous fash-
ion. A 16 bit address bus for x4 and x8 organised compo-
nents and a 15 bit address bus for x16 components is used to
convey row, column, and bank address devices.
REV 2.3
06/2008
Speed Sorts
Bin
max. Clock
Frequency
Data Rate
CAS Latency
t
t
t
RCD
RP
RC
• 1.8V ± 0.1V Power Supply Voltage
• 4 internal memory banks
• Programmable CAS Latency: 3, 4 and 5
(CL-tRCD-TRP)
DDR2
3-3-3
-400
200
400
-5A
15
15
55
3
DDR2
4-4-4
-37B
-533
266
533
15
15
60
4
DDR2
5-5-5
-667
333
667
-3C
15
15
60
NT5TU64M8AB
5
Mb/s/pin
Units
MHz
tck
tck
ns
ns
ns
1
NT5TU32M16AF
These devices operate with a single 1.8V +/-0.1V power sup-
ply and are available in BGA packages.
An Auto-Refresh and Self-Refresh mode is provided along
with various power-saving power-down modes.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
• Programmable Additive Latency: 0, 1, 2, 3 and 4
• Write Latency = Read Latency -1
• Programmable Burst Length: 4 and 8
• Programmable Sequential / Interleave Burst
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• 4 bit prefetch architecture
• 1KB page size for x 4 & x 8,
• Data-Strobes: Bidirectional, Differential
• Strong and Weak Strength Data-Output Driver
• Auto-Refresh and Self-Refresh
• Power Saving Power-Down modes
• 7.8 µs max. Average Periodic Refresh Interval
2KB page size for x16
Packages:
60 pin BGA for x4/x8 components
84 pin BGA for x8/x16 components
©
NANYA TECHNOLOGY CORP
. All rights reserved.

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