EDD1232ABBH-5C-E Elpida Memory, Inc., EDD1232ABBH-5C-E Datasheet
EDD1232ABBH-5C-E
Manufacturer Part Number
EDD1232ABBH-5C-E
Description
DDR 4Mx32, 400MHz, BGA-144, leadfree
Manufacturer
Elpida Memory, Inc.
Specifications of EDD1232ABBH-5C-E
Package
Tray/JP
Unit
800
Date_code
07+
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Specifications
• Density: 128M bits
• Organization
⎯ 1M words × 32 bits × 4 banks
• Package: 144-ball FBGA
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 2.5V ± 0.125V
• Data rate: 400Mbps (max.)
• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
⎯ Sequential (2, 4, 8)
⎯ Interleave (2, 4, 8)
• /CAS Latency (CL): 3
• Precharge: auto precharge operation for each burst
• Driver strength: weak/matched
• Refresh: auto-refresh, self-refresh
•
⎯ Average refresh period: 7.8μs
• Operating ambient temperature range
⎯ TA = 0°C to +70°C
Document No. E0874E40 (Ver. 4.0)
Date Published April 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
access
Refresh cycles: 4096 cycles/32ms
EDD1232ABBH (4M words × 32 bits)
128M bits DDR SDRAM
DATA SHEET
Features
• ×32 organization
• Double-data-rate architecture; two data transfers per
• The high-speed data transfer is realized by the 2 bits
• Bi-directional data strobe (DQS) is transmitted
• Data inputs, outputs, and DM are synchronized with
• DQS is edge-aligned with data for READs; center-
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
• Commands entered on each positive CK edge; data
• Data mask (DM) for write data
clock cycle
prefetch pipelined architecture
/received with data for capturing data at the receiver
DQS
aligned with data for WRITEs
transitions
and data mask referenced to both edges of DQS
©Elpida Memory, Inc. 2006-2007
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