EDJ4204BASE-DJ-F Elpida Memory, Inc., EDJ4204BASE-DJ-F Datasheet

EDJ4204BASE-DJ-F

Manufacturer Part Number

EDJ4204BASE-DJ-F

Description

DDR3 4GBit (1Gx4), FBGA78, leadfree

Manufacturer

Elpida Memory, Inc.

Datasheet

1.EDJ4208BASE-DJ-F.pdf (147 pages)

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Specifications

Document No. E1705E40 (Ver. 4.0)

Date Published May 2011 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Density: 4G bits

Organization

Package

Power supply: VDD, VDDQ

Data rate

1KB page size

Eight internal banks for concurrent operation

Interface: SSTL_15

Burst lengths (BL): 8 and 4 with Burst Chop (BC)

Burst type (BT):

/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

/CAS Write Latency (CWL): 5, 6, 7, 8

Precharge: auto precharge option for each burst

access

Driver strength: RZQ/7, RZQ/6 (RZQ = 240 )

Refresh: auto-refresh, self-refresh

Refresh cycles

Operating case temperature range

128M words

64M words

78-ball FBGA

Lead-free (RoHS compliant) and Halogen-free

1600Mbps/1333Mbps/1066Mbps (max.)

Row address: A0 to A15

Column address: A0 to A9, A11 (EDJ4204BASE)

Sequential (8, 4 with BC)

Interleave (8, 4 with BC)

Average refresh period

7.8 s at 0 C

3.9 s at 85 C

TC = 0 C to +95 C

8 bits

4 bits

EDJ4204BASE (1024M words 4 bits)

A0 to A9 (EDJ4208BASE)

EDJ4208BASE (512M words 8 bits)

8 banks (EDJ4208BASE)

85 C

8 banks (EDJ4204BASE)

95 C

4G bits DDR3 SDRAM

1.5V

0.075V

DATA SHEET

Features

Double-data-rate architecture: two data transfers per

clock cycle

The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

Differential clock inputs (CK and /CK)

DLL aligns DQ and DQS transitions with CK

transitions

Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

Data mask (DM) for write data

Posted /CAS by programmable additive latency for

better command and data bus efficiency

On-Die Termination (ODT) for better signal quality

Multi Purpose Register (MPR) for pre-defined pattern

read out

ZQ calibration for DQ drive and ODT

Programmable Partial Array Self-Refresh (PASR)

/RESET pin for Power-up sequence and reset

function

SRT range:

Programmable Output driver impedance control

Synchronous ODT

Dynamic ODT

Asynchronous ODT

Normal/extended

Elpida Memory, Inc. 2010-2011

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