ASC7611 ETC2 [List of Unclassifed Manufacturers], ASC7611 Datasheet - Page 32

• Manufacturer Part Number: ASC7611
• Description: HARDWARE MONITOR WITH INTEGRATED FAN CONTROL
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Register 6A-6Ch: Temperature Limit
Register
Address
In the Auto Fan mode, if a zone exceeds the temperature set in the Absolute Temperature Limit register, all of the PWM
outputs will increase its duty cycle to 100%. This is a safety feature that attempts to cool the system if there is a potentially
catastrophic thermal event. If set to 80h (-128°C), the feature is disabled. Default = 100 C = 64h. The PWM will remain at
100% until the assigned zone temperature falls below the Absolute Temp Limit for that zone by an amount equal to the
hysteresis value for that zone.
These registers become read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write
to these registers shall have no effect.
Register
Address
If the temperature is above Fan Temp Limit, then drops below Fan Temp Limit, the following will occur:
This register becomes read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to
these registers shall have no effect.
© Andigilog, Inc. 2006
Register 6D-6Eh: Thermal Zone Hysteresis
6Ah
6Bh
6Ch
6Dh
6Eh
•
•
The fan will remain on, at Fan PWM Minimum, until the temperature goes a certain amount below Fan Temp Limit.
The Hysteresis registers control this amount. See below table for details, all values from 0°C to 15°C are possible.
Read/
Read/
Write
Write
R/W
R/W
R/W
R/W
R/W
Zone 1 Temp
Absolute Limit
Zone 2 Temp
Absolute Limit
Zone 3 Temp
Absolute Limit
Zone 1 and
Zone 2
Hysteresis
Zone 3
Hysteresis
Register
Register
Name
Name
Table 18 Absolute Temperature Limit Register -
(MSB)
(MSB)
Bit 7
Bit 7
H1-3
H3-3
7
7
7
-128°C (Disable)
+100°C (default)
Temperature
Bit 6
Bit 6
H1-2
H3-2
>127°C
+127°C
+125°C
-127°C
+50°C
+25°C
-50°C
8-Bit Two’s Complement
6
6
6
0°C
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Bit 5
Bit 5
H1-1
H3-1
5
5
5
- 32 -
Bit 4
Bit 4
H1-0
H3-0
(2’s Complement)
4
4
4
0111
0111
0111
0110
0011
0001
0000
1100
1000
1000
Absolute Limit
Bit 3
Bit 3
H2-3
RES
3
3
3
1111
1111
1101
0100
0010
1001
0000
1110
0001
0000
Bit 2
Bit 2
H2-2
RES
2
2
2
Bit 1
Bit 1
H2-1
RES
1
1
1
October 2006 - 70A05007
(LSB)
(LSB)
Bit 0
Bit 0
H2-0
RES
0
0
0
aSC7611
Default
Default
Value
Value
64
64
64
44
40
Lock
Lock
X
X
X
X
X