K9F5608Q0C SAMSUNG [Samsung semiconductor], K9F5608Q0C Datasheet
K9F5608Q0C
Related parts for K9F5608Q0C
K9F5608Q0C Summary of contents
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... NAND Flash Errata Description : Some of AC characteristics are not meeting the specification > AC characteristics : Refer to Table Affected Products : K9F1208Q0A-XXB0, K9F1216Q0A-XXB0 K9F5608Q0C-XXB0, K9F5616Q0C-XXB0 K9K1208Q0C-XXB0, K9K1216Q0C-XXB0 Improvement schedule : The components without this restriction will Workaround : Relax the relevant timing parameters according to the table. ...
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... Program : Icc2 20mA-->25mA Erase : Icc3 20mA-->25mA 2.1 The min. Vcc value 1.8V devices is changed. K9F56XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V 2.2 Pb-free Package is added. K9F5608U0C-FCB0,FIB0 K9F5608Q0C-HCB0,HIB0 K9F5616U0C-HCB0,HIB0 K9F5616U0C-PCB0,PIB0 K9F5616Q0C-HCB0,HIB0 K9F5608U0C-HCB0,HIB0 K9F5608U0C-PCB0,PIB0 2.3 Errata is added.(Front Page)-K9F56XXQ0C tWC tWH tWP tRC tREH tRP tREA tCEA ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 32M x 8 Bit / 16M x 16 Bit NAND Flash Memory PRODUCT LIST Part Number K9F5608Q0C-D,H K9F5616Q0C-D,H K9F5608U0C-Y,P K9F5608U0C-D,H K9F5608U0C-V,F K9F5616U0C-Y,P K9F5616U0C-D,H FEATURES Voltage Supply - 1.8V device(K9F56XXQ0C) : 1.70~1.95V - 3.3V device(K9F56XXU0C) : 2.7 ~ 3.6 V Organization - Memory Cell Array - X8 device(K9F5608X0C) : (32M + 1024K)bit x 8 bit - X16 device(K9F5616X0C) : (16M + 512K)bit x 16bit ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 PIN CONFIGURATION (TSOP1) X16 X8 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C R/B R N.C N.C N.C N.C Vcc Vcc Vss Vss N.C N.C N.C N.C CLE CLE ALE ALE N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 ¡Æ 0~8 0.45~0.75 0.018~0.030 K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616U0C-YCB0,YIB0,PCB0,PIB0 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 PIN CONFIGURATION (TBGA N.C N.C N.C A /WP ALE Vss / /RE CLE I/ I/O1 NC VccQ I/O5 H Vss I/O2 I/O3 I/O4 N.C N.C Top View N.C N.C PACKAGE DIMENSIONS 63-Ball TBGA (measured in millimeters) Top View 9.00 0.10 #A1 K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616U0C-YCB0,YIB0,PCB0,PIB0 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 PIN CONFIGURATION (WSOP1) N.C N.C DNU N.C N.C N.C R DNU N.C Vcc Vss N.C DNU CLE ALE WE WP N.C N.C DNU N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F #1 #24 K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616U0C-YCB0,YIB0,PCB0,PIB0 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-VCB0,FCB0/VIB0,FIB0 ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 PIN DESCRIPTION Pin NAME DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The 0 7 (K9F5608X0C) I/O pins float to high-z when the chip is deselected or when the outputs are disabled. I/O ~ I/O I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper- ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 Figure 1-1. K9F5608X0C (X8) FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-1. K9F5608X0C (X8) ARRAY ORGANIZATION 64K Pages 1st half Page Register ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 Figure 1-2. K9F5616X0C (X16) FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-2. K9F5616X0C (X16) ARRAY ORGANIZATION 64K Pages ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 PRODUCT INTRODUCTION The K9F56XXX0C is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528(X8 device) or 264(X16 device) columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8 device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F56XXX0C-XCB0 Temperature Under Bias K9F56XXX0C-XIB0 K9F56XXX0C-XCB0 Storage Temperature K9F56XXX0C-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 VALID BLOCK Parameter Valid Block Number NOTE : K9F56XXX0C 1. The may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits or program factory-marked bad blocks ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time NOTE : 1 ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 Pointer Operation of K9F5608X0C(X8) Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’ 00h’ command sets the pointer to ’ A’ area(0~255byte), ’ 01h’ command sets the pointer to ’ B’ area(256~511byte), and ’ 50h’ command sets the pointer to ’ ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 Pointer Operation of K9F5616X0C(X16) Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’ 00h’ command sets the pointer to ’ A’ area(0~255word), and ’ 50h’ command sets the pointer to ’ B’ area(256~263word). With these commands, the starting column address can be set to any of a whole page(0~263word). ’ ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 System Interface Using CE don’ t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte/264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addi- tion, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 Device K9F5608X0C(X8 device) K9F5616X0C(X16 device) NOTE: 1. I/O8~15 must be set to "0" during command or address input. 2. I/O8~15 are used only for data bus. * Command Latch Cycle CLE CE WE ALE I/Ox * Address Latch Cycle CLE ALE I/Ox K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616U0C-YCB0,YIB0,PCB0,PIB0 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 I/O I/ ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 * Input Data Latch Cycle CLE CE t ALS ALE I/Ox * Sequential Out Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load. K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616U0C-YCB0,YIB0,PCB0,PIB0 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 DIN 0 ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 * Status Read Cycle CLE I/Ox READ1 OPERATION (READ ONE PAGE) CLE ALE RE N Address Read I/Ox A0~A7 CMD Column Address R/B X8 device : m = 528 , Read CMD = 00h or 01h X16 device : m = 264 , Read CMD = 00h K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616U0C-YCB0,YIB0,PCB0,PIB0 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 t CLR t CLS ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE RE N Address Read I/Ox Col. Add CMD Column Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE I/Ox 50h Col. Add R/B M Address X8 device : A X16 device : A K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616U0C-YCB0,YIB0,PCB0,PIB0 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 On K9F5608U0C_Y,P or K9F5608U0C_V,F CE must be held ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 SEQUENTIAL ROW READ OPERATION CLE CE WE ALE RE 00h Row Add1 I/Ox Col. Add R/B M PAGE PROGRAM OPERATION CLE ALE RE N Address I/Ox 80h Col. Add Row Add1 Sequential Data Column Input Command Address R/B K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616U0C-YCB0,YIB0,PCB0,PIB0 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 (only for K9F5608U0C-Y,P or K9F5608U0C-V,F) ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 COPY-BACK PROGRAM OPERATION CLE ALE RE I/Ox 00h Col. Add Row Add1 Column Page(Row) Address Address R/B BLOCK ERASE OPERATION CLE ALE RE I/Ox 60h A9~A16 Page(Row) Address R/B Auto Block Erase Setup Command K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616U0C-YCB0,YIB0,PCB0,PIB0 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 8Ah ...
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... K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I/Ox 90h Read ID Command K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616U0C-YCB0,YIB0,PCB0,PIB0 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 REA 00h Address. 1cycle Device K9F5608Q0C K9F5608U0C K9F5616Q0C K9F5616U0C 25 FLASH MEMORY Device ECh Code* Maker Code Device Code Device Code* 35h 75h XX45h XX55h ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg- ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 Figure 9. Read2 Operation CLE CE WE ALE R/B RE I/Ox Start Add.(3Cycle) 50h X8 device : X16 device : device : Don’ t care 4 7 X16 device : are "L" Figure 8-1. Sequential Row Read1 Operation (only for K9F5608U0C-Y,P or K9F5608U0C-V,F) ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 Figure 9-1. Sequential Row Read2 Operation (only for K9F5608U0C-Y,P or K9F5608U0C-V,F) R/B I/Ox Start Add.(3Cycle) 50h & Don t Care) K9F5616Q0C-DCB0,DIB0,HCB0,HIB0 K9F5616U0C-YCB0,YIB0,PCB0,PIB0 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 Data Output 1st ~ Data Field Spare Field 28 FLASH MEMORY t R Data Output ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive bytes/words up to 528 264 (X8 device) or ming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com- mand(60h). Only address address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... K9F5616U0C-YCB0,YIB0,PCB0,PIB0 K9F5616U0C-DCB0,DIB0,HCB0,HIB0 t CEA WHR1 REA 00h Address. 1cycle t RST After Power-up Read 1 31 FLASH MEMORY Device ECh Code* Maker code Device code Device Device Code* K9F5608Q0C 35h K9F5608U0C 75h K9F5616Q0C 45h K9F5616U0C 55h After Reset Waiting for next command ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 > In high state of LOCKPRE pin, Block lock mode and Power on Auto read are enabled, otherwise it is regarded as NAND Flash without LOCKPRE pin. Block Lock Mode Block Lock mode is enabled while LOCKPRE pin state is high, which is to offer protection features for NAND Flash data. The Block Lock mode is divided into Unlock, Lock, Lock-tight operation ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 2) Unlock - Command Sequence: Unlock block Command(23h) + Start block address + Command(24h) + End block address - Unlocked blocks can be programmed or erased unlocked block’ s status can be changed to the locked or lock-tighten state using the appropriate commands. - Only one consecutive area can be released to unlock state from lock state; Unlocking multi area is not available. ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 Unlock block Command (23h) + Start Block Address Block Lock reset WPx = H & WPx = L (>100ns) Lock block command (2Ah) WPx = H & Lock-tight block command (2Ch) Program/Erase OPERATION(In Locked or Lock-tighten Block) R/B I/Ox Address(&Data Input) 60h(80h) On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10 s( ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 2. Block Lock Status Read Block Lock Status can be read on a block basis, which may be read to find out whether designated block is available to be pro- grammed or erased. After writing 7Ah command to the command register. and block address to be checked, a read cycle outputs the content of the Block Lock Status Register to the I/O pins on the falling edge RE, whichever occurs last ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 Power-On Auto-Read The device is designed to offer automatic reading of the first page without command and address input sequence during power-on. An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. LOCKPRE pin controls activation of auto- page read function. Auto-page read function is enabled only when LOCKPRE pin is logic high state after power-on without latency ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... K9F5608U0C-VCB0,VIB0,FCB0,FIB0 K9F5608Q0C-DCB0,DIB0,HCB0,HIB0 K9F5608U0C-YCB0,YIB0,PCB0,PIB0 K9F5608U0C-DCB0,DIB0,HCB0,HIB0 Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device) or 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down and recovery time of minimum required before internal IL circuit gets ready for any command sequences as shown in Figure 18 ...