ATA3742_07 ATMEL [ATMEL Corporation], ATA3742_07 Datasheet
ATA3742_07
Related parts for ATA3742_07
ATA3742_07 Summary of contents
Page 1
Features • IC Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal Strength Indicator) Output • Minimal External Circuitry Requirements Components on the PC Board Except Matching to the Receiver Antenna • High Sensitivity, Especially at ...
Page 2
Figure 1-1. System Block Diagram UHF ASK/FSK Remote control transmitter 1 Li cell U2741B Encoder ATARx9x Keys XTO Figure 1-2. Block Diagram FSK/ASK CDEM RSSI SENS AVCC AGND DGND MIXVCC LNAGND LNA_IN ATA3742 2 PLL Antenna Antenna VCO Power amp. ...
Page 3
Pin Configuration Figure 2-1. Pinning SO20 Table 2-1. Pin Description Pin Symbol Function 1 SENS Sensitivity-control resistor Selecting FSK/ASK 2 FSK/ASK Low: FSK, High: ASK 3 CDEM Lower cut-off frequency of the data filter 4 AVCC Analog power supply ...
Page 4
RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1 MHz IF signal. As seen in amplifier), LO (local oscillator), a mixer and an RF amplifier. The ...
Page 5
To determine f frequency tuned by the crystal frequency f f that depends on the logic level at pin MODE. This is described by the following formulas: LO MODE MODE The relation is designed to achieve the ...
Page 6
Figure 3-2. Input Matching Network With SAW Filter 433.92 MHz RF TOKO ® LL2012 RF F33NJ IN_GND 8.2 pF Figure 3-3. ...
Page 7
Analog Signal Processing 4.1 IF Amplifier The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter ...
Page 8
Figure 4-1. Figure 4- Sense is defined by the value of R input. The reduced sensitivity is dependent on the signal strength at the output of the RSSI amplifier. Since different RF input networks may exhibit slightly different ...
Page 9
R Sense full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the ...
Page 10
Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (t These limits are defined in the electrical characteristics. They should not be exceeded to main- tain full sensitivity of the receiver. 4.5 Receiving Characteristics The RF ...
Page 11
Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor- responding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically ...
Page 12
Most applications are dominated by two transmission frequencies: f used in the USA, f parameters, the electrical characteristics display three conditions for each parameter. • Application USA (f • Application Europe (f • Other applications (T electrical characteristic is given ...
Page 13
Sleep Mode The length of period T sion factor X calculated to be Sleep Sleep In US and European applications, the maximum value “1”. The time resolution is about that case. ...
Page 14
Figure 5-2. For best noise immunity it is recommended to use a low span between T This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A “11111...” or “10101...” sequence in Manchester or ...
Page 15
Figure 5-3. Polling Mode Flow Chart Sleep Mode: All circuits for signal processing are disabled. Only XTO and Polling logic are enabled. Output level on pin IC_ACTIVE = > low Soff T = Sleep Sleep Start-up ...
Page 16
Figure 5-4. Timing Diagram for Complete Successful Bit Check (Number of checked Bits: 3) Enable IC Bit check Dem_out Data Startup mode Figure 5-5. Timing Diagram During Bit Check (Lim_min = 14, Lim_max = 24) Enable IC T Startup Bit ...
Page 17
Figure 5-5 on page 16 Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during T that period. When the bit check becomes active, the bit check counter is clocked with ...
Page 18
Figure 5-8. Synchronization of the Demodulator Output T XClk Clock bit check counter Dem_out DATA Figure 5-9. Debouncing of the Demodulator Output Dem_out DATA Lim_min Figure 5-10. Steady L State Limited DATA Output Pattern after Transmission Enable IC Bit check ...
Page 19
Switching the Receiver Back to Sleep Mode The receiver can be set back to polling mode via pin DATA or via pin ENABLE. When using pin DATA, this pin must be pulled to Low for the period t controller. ...
Page 20
Figure 5-12. Timing Diagram of the OFF Command via Pin ENABLE ENABLE DATA (ATA3742) Serial bi-directional data line Receiving mode 5.4 Configuration of the Receiver The ATA3742 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The ...
Page 21
Table 5-2. Effect of the Configuration Words Within the Registers Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 OFF Command 1 OPMODE Register 0 1 BR_Range 0 1 Baud1 Baud0 BitChk1 (Default LIMIT Register 0 ...
Page 22
Table 5-6. Effect of the Configuration Word Sleep Sleep Sleep4 Sleep3 Sleep2 ...
Page 23
Table 5-9. Effect of the Configuration Word Lim_max Lim_max Lim_max < not applicable ...
Page 24
Figure 5-13. Generation of the Power-on Reset V S POR X DATA (ATA3742) Figure 5-14. Timing of the Register Programming Out1 (microcontroller) DATA (ATA3742) X Serial bi-directional X data line Receiving mode 5.4.2 Programming the Configuration Register The configuration registers ...
Page 25
To start programming, the serial data line DATA is pulled to “L” for the time period t microcontroller. When DATA has been released, the receiver becomes the master device. When the programming delay period t with the pulse length t ...
Page 26
Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated ...
Page 27
Electrical Characteristics (Continued) All parameters refer to GND –40°C to +105°C, V amb ( 25°C) S amb Parameter Test Condition Symbol Receiving Mode Intermediate MODE=0 (USA) frequency MODE=1 (Europe) BR_Range0 Baud-rate BR_Range1 BR_Range ...
Page 28
Electrical Characteristics (Continued) All parameters refer to GND –40°C to +105°C, V amb ( 25°C) S amb Parameter Test Condition Symbol Synchroni-zati on pulse (Figure 5-11 on page 19, Figure 5-14 on page ...
Page 29
Electrical Characteristics All parameters refer to GND –40°C to +105°C, V amb ( 25°C) S amb Parameters Current consumption LNA Mixer Third-order intercept point LO spurious emission Noise figure LNA ...
Page 30
Electrical Characteristics (Continued) All parameters refer to GND –40°C to +105°C, V amb ( 25°C) S amb Parameters Static capacitance of the crystal Analog Signal Processing Input sensitivity ASK Input sensitivity ASK Sensitivity ...
Page 31
Electrical Characteristics (Continued) All parameters refer to GND –40°C to +105°C, V amb ( 25°C) S amb Parameters Lower cut-off frequency of the data filter Recommended CDEM for best performance Recommended CDEM for ...
Page 32
Electrical Characteristics (Continued) All parameters refer to GND –40°C to +105°C, V amb ( 25°C) S amb Parameters Threshold voltage for reset Digital Ports Data output - Saturation voltage LOW - Internal pull-up ...
Page 33
Ordering Information Extended Type Number ATA3742P3-TGSY ATA3742P3-TGQY 11. Package Information Package SO20 Dimensions in mm 0.4 1. 12. Revision History Please note that the following page numbers referred to in this section refer to the specific revision ...
Page 34
Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to ...