H5PS1G63EFR HYNIX [Hynix Semiconductor], H5PS1G63EFR Datasheet - Page 23
H5PS1G63EFR
Manufacturer Part Number
H5PS1G63EFR
Description
1Gb DDR2 SDRAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
1.H5PS1G63EFR.pdf
(44 pages)
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Rev. 0.4 / Nov 2008
Four Active Window for 1KB page size
products
Four Active Window for 2KB page size
products
CAS to CAS command delay
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-
read command
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(HIGH and LOW pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after
CKE asynchronously drops LOW
Parameter
tFAW
tFAW
tCCD
tWR
tDAL
tWTR
tRTP
tXSNR
tXSRD
tXP
tXARD
tXARDS
tAONPD
Symbol
tAOFPD
tAOND
tAOFD
tANPD
tAXPD
tDelay
tCKE
tAON
tAOF
tOIT
tRFC + 10
tAC(min)+
tAC(min)+
tIS+tCK+tI
WR+tRP*
tAC(min)
tAC(min)
6 - AL
min
37.5
200
7.5
2.5
50
15
10
H
2
2
2
3
2
2
2
3
8
0
DDR2-400
2.5tCK+tA
2tCK+tAC
C(max)+1
tAC(max)
tAC(max)
(max)
+ 0.6
max
2.5
+1
+1
12
2
-
-
-
-
-
-
-
tIS+tCK+tI
tRFC + 10
tAC(min)+
tAC(min)+
WR+tRP*
tAC(min)
tAC(min)
6 - AL
37.5
min
200
7.5
7.5
2.5
50
15
H
0
2
2
3
2
2
2
3
8
2
DDR2-533
C(max)+1
tAC(max)
tAC(max)
AC(max)
2.5tCK+t
2tCK+tA
+ 0.6
max
2.5
+1
+1
12
2
-
-
-
-
-
-
-
H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
-Continued-
Units
ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
17,44
17,44
1, 2
14
24
27
16
16
15
3
1
23