HM17CM256 HYNIX [Hynix Semiconductor], HM17CM256 Datasheet - Page 13
HM17CM256
Manufacturer Part Number
HM17CM256
Description
128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
1.HM17CM256.pdf
(111 pages)
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PIN DESCRIPTION 4
164~169,
162~137,
568~594,
132~119,
174~557
562~567
3~15
163
65,
No.
16
66
64
(port No. 1,2,133,134,135,136,170,171,172,173,558,559,560,561,595,596 is dummy port.)
SEGSA
SEGSB
SEGSC
SEGB
SEGA
SEGC
COM
NAME
COMI
COMI
OSC
OSC
0
0
CLK
0
~SEGA
~SEGB
0
0
0
~SEGC
0
~COM
~SEGSA
~SEGSB
~SEGSC
1
2
0
1
,
79
127
127
127
3
,
3
,
3
,
,
I/O
I/O
O
O
O
O
O
O
I
Segment drive port
(B/W mode)
Dummy segment driver output
Common driver output
Common drive output for icon display
Common drive output for icon display
External reference clock input pin
Input / output pin for display timing clock
display RAM data
Segment output from display RAM data
The output level is selected among V
combination of FR signal and RAM data
Reverse mode
Located at both side of segment drivers, used for edge
display.
The output level is selected among V
the combination of FR and scan data.
Open when using internal oscillator clock or used as slave
device.
In this case, OSC
Connect external oscillating source to OSC
resistor between OSC
oscillator.
Output clock from master device is applied to slave chip
through CLK pin when used as master / slave mode.
Normal mode
M/S
FR signal
H
L
data
Reverse
Normal
H
H
L
L
mode
master
mode
slave
1
FR
H
H
L
L
goes to V
Non-lighted
FUNCTION
V
1
*input from master chip’s CLK output
V
LCD
and OSC
2
0
1
output
SS
input*
CLK
V
level.
Output level
V
LCD
2
V
V
V
V
HM17CM256
2
LCD
SS
LCD
1
4
LCD
V
V
when using external
SS
lighted
3
, V
, V
1
0
1
1
2
, V
, V
V
port or connect
V
SS
4
3
3
and V
, V
SS
by the
SS
- 13 -
by
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