HM17CM256 HYNIX [Hynix Semiconductor], HM17CM256 Datasheet - Page 34

• Manufacturer Part Number: HM17CM256
• Description: 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
• Manufacturer: HYNIX [Hynix Semiconductor]

HM17CM256
(14) DISPLAY TIMMING GENERATOR
(15) SIGNAL GENERATION OF DISPLAY LINE COUNTER, DISPLAY DATA LATCH CIRCUIT.
(16) GENERATION OF THE ALTERNATED SIGNAL(FR), SYNCHRONOUS SIGNAL(FLM).
(17) DISPLAY DATA LATCH CIRCUIT
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internal operation by inputting the original oscillating clock CK or by the oscillating circuit.
changes.
(CL). Synchronized with the display clock, the line addresses of Display RAM are generated and
384-bit display data are latched to display-data latching circuit and then output to the LCD drive
circuit (SEG output port).
MPU can access it with no relationship with the read-out operation of the display data.
(CL). The FLM generates alternated drive waveform to the LCD drive circuit per frame at normal
state ( inverse FR signal level per 1 frame ). But by setting up data (n-1) on n-line inversion
register and “1” on n-line alternated command (NLIN), n-line inverse waveform can be generated.
must be sent from master side to slave side.
common period. Normal / reverse display, display ON/OFF, and display all on command are done
by controlling data in this latch. And no data within display RAM changes.
The display-timing generator makes a timing clock and timing pulses (CL, FLM, FR and CLK) for
By setting up Master / Slave mode (M/S), the state of timing pulse pins and the timing generator
The latch signal from line counter clock to display data latch circuit is generated from display clock
Read-out of the display data to the LCD drive circuit is completely independent of MPU side and so
The alternated signal (FR) and synchronous signal (FLM) are generated from the display clock
When this HM17CM256 is used in multi-chip application, the signals of CL, FLM, FR and CLK
This circuit latches the display data from display RAM to LCD driver circuit temporarily per every
M/S port
H
L
Display timing pulse pins and generator status
Master
mode
Slave
CL port
Output
Input
FR port
Output
Input
FLM port CLK port
Output
Input
Output
Input
CL, FLM, FR signal generator stop
Timing generator status
Operating status