K9K1208D0C Samsung semiconductor, K9K1208D0C Datasheet - Page 24
K9K1208D0C
Manufacturer Part Number
K9K1208D0C
Description
64M x 8 Bit / 32M x 16 Bit NAND Flash Memory
Manufacturer
Samsung semiconductor
Datasheet
1.K9K1208D0C.pdf
(25 pages)
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DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V
during power-up and power-down as shown in Figure 11. The two step command sequence for program/erase provides additional
software protection.
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by the following equation.
Figure 11. AC Waveforms for Power Transition
K9F8008W0M-TCB0, K9F8008W0M-TIB0
V
WP
CC
V
CC
GND
Device
~ 2.5V
R/B
open drain output
High
where I
R/B pin.
Rp =
Note* : 5.1V when Vcc=3.6V~5.5V
24
L
3.2V when Vcc=2.7V~3.6V
V
is the sum of the input currents of all devices tied to the
CC
(Max.) - V
I
OL
+ I
OL
L
(Max.)
FLASH MEMORY
=
~ 2.5V
8mA + I
Note*
L
IL