ZL10036LDF ZARLINK [Zarlink Semiconductor Inc], ZL10036LDF Datasheet
ZL10036LDF
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ZL10036LDF Summary of contents
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... Digital Satellite Tuner with RF Bypass Ordering Information ZL10036LDG ZL10036LDF ZL10036LDG1 40-pin QFN* ZL10036LDF1 40-pin QFN* Description The ZL10036 is a single chip wideband direct conversion tuner, with integral RF bypass, optimized for application in digital satellite receiver systems. The device offers a highly integrated solution to a satellite tuner function, incorporating an I² ...
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Figure 2 - Typical Application Circuit ZLE10532 (SNIM-9r2) using ZL10312 Demodulator ZL10036 2 Zarlink Semiconductor Inc. Data Sheet ...
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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical characteristics ...
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Figure 1 - Basic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Pins by Number Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin Listings No. Name 1 QDC 2 QDC 3 QOUT 4 QOUT 5 VccBB 6 VccBB 7 IOUT 8 IOUT 9 IDC 10 IDC Name No. ADD 16 CNT 40 DIGDEC 17 DRIVE 20 IDC 9 IDC 10 IOUT 7 ...
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Pin Description Pin Symbol Direction 1 QDC NA 2 QDC NA 3 QOUT Out 4 QOUT Out 5 VccBB 6 VccBB 7 IOUT Out 8 IOUT Out 9 IDC NA 10 IDC NA 11 SLEEP In 12 SCL In 13 ...
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Pin Symbol Direction 14 XTAL In 15 XTALCAP Out 16 ADD In 17 DIGDEC Out 18 VccDIG 19 VccTune 20 DRIVE IO 21 PUMP IO 22 N/C 23 Vvar In ZL10036 Function Reference oscillator crystal inputs. Selected crystal frequency must ...
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Pin Symbol Direction 24 P0 Out 25 LOCK Out 26 VccRF 27 RFBYPASS Out 28 RFBYPASS Out 29 VccRF 30 N/C 31 RFIN In 32 RFIN In 33 N/C 34 RFAGC In ZL10036 Function Switching port P0. ‘0’ = disabled ...
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Pin Symbol Direction 35 PTEST In 36 VccLO 37 VccLO 38 LOTEST Out 40 CNT Note: Exposed paddle on rear of package must be connected to GND 1.0 Overview 1.1 Conventions in this Manual Hexadecimal values are ...
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Functional Description 2.1 Quadrature Down-Converter In normal applications the tuner RF input frequency of 950 - 2150 MHz is fed directly to the ZL10036 RF input preamplifier stage, through an appropriate impedance match. The input preamplifier is optimized for ...
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The baseband post-filter gain stage can be used to provide additional gain to maintain desired output amplitude with lower symbol rate applications. Normalized gain range in dB: Gain function: RF AGC Control Analogue function: voltage 2.2.1 RF ...
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Figure 6 - Variation in IIP2 with AGC setting (RF gain adjust = +0 dB, prefilter = +4.2 dB and postfilter = 4.2 dB, baseband filter bandwidth = ...
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RF programmable gain = prefilter gain = 4.2 dB filter gain = aseband o utput level = 0.5 Vp -90 Figure 8 - Variation ...
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RF bypass The ZL10036 provides an independent bypass function, which can be used for driving a second receiver module. The electrical characteristics of the RF input are unchanged by the state of the RF bypass. The bypass provides a ...
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Baseband Filter The filter bandwidth is controlled by a Frequency Locked Loop (FLL) the timing of which is derived from the reference crystal source by a reference divider. Five control bits set the system reference division ratio and the ...
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Local Oscillator The LO on the ZL10036 is fully integrated and consists of three oscillator stages. These are arranged such that the regions of operation for optimum phase noise are contiguous over the required tuning range of 950 to ...
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Control Logic The ZL10036 is controlled by an I²C data bus and can function as a slave receiver or slave transmitter compatible with 3V3 levels. Data and Clock are input on the SDA and SCL lines ...
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Device Address Selection Two internal logic levels, MA1 and MA0, can be set to one of four possible logic states by the voltage applied to the ADD pin (#16). These four states in turn define four different read and ...
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Internal Operation Indicators (X Bits) These bits indicate internal logic states and are not required for normal use of the ZL10036. 3.4 Write Registers The ZL10036 has twelve registers which can be programmed by addressing the device in its ...
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Register Mapping Bit No. 7 (MSB) Function Byte 1 Device address Programmable Divider BF6 8 1 Control Data ...
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Synthesizer Division Ratio (2 The PLL synthesizer interfaces with the LO multiplex output and runs at the desired frequency for down-conversion. The step size at the desired conversion frequency, is equal to the loop comparison frequency. The programmable division ...
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RF Bypass Disable (LEN Bit) The RF bypass function is disabled by setting LEN, bit-0 of register byte logic ‘1’. By default, this bit logic ‘0’ at power-up, and therefore the function is enabled. ...
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Reference Division Ratios (R4:0 Bits) Register bits R4:0 control the reference divider ratios as shown in Table 13. They are programmed through bit-4 to bit-0 respectively, in byte- Table 13 ...
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Software In normal operation, only initialization, channel (frequency) changes and symbol rates require programming intervention. Note that the PLL comparison frequency is set by the crystal frequency divided by the PLL reference divide ratio. In the following examples of ...
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Calculating the Filter Bandwidth The -3 dB bandwidth of the filter (Hz) is given by the following expression: f xtal Equation 1 - --------- - Where Baseband filter –3 dB bandwidth (Hz) which ...
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Filter Bandwidth Programming Examples f Example 1, conditions: = 10.111MHz, xtal f Because is below 28.2MHz, the value of BR can be evaluated with equation 10.111MHz xtal BR = ------------------- - = ----------------------------- - = 17.583 ...
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Application Notes 5.1 Thermal Considerations Figure 12 - Copper Dimensions for Optimum Heat Transfer Figure 13 - Paste Mask for Reduced Paste Coverage The ZL10036 uses the 40-pin QFN package with a thermal ‘paddle’ in the base, which has ...
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To transfer the heat from the paddle to the underside of the board, an array 0·3 mmØ vias are used between the topside pad, which will be ...
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Electrical characteristics 6.1 Test Conditions The following conditions apply to all figures in this chapter, except where notes indicate other settings. Tamb = -10° to 85°C, Vee All Vcc supplies = 5 V±5% RF gain adjust = ...
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Recommended Operating Conditions Parameter Supply voltage Operating temperature 6.4 DC Characteristics Pins Characteristic All Vcc pins 18, 19, Supply current 26, 29, 36, 37 Output impedance QOUT, Output load QOUT, IOUT, IOUT QDC, ...
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Pins Characteristic Max. voltage DRIVE: 20 Min. voltage XTAL, Recommended XTALCAP: crystal E.S.R. 14, 15 Input current Vvar: 23 Sink current P0, P1: 24, 39 Leakage current Low output voltage LOCK: 25 High output voltage Load current Input high current ...
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Characteristic System IM2 System IM3 Variation in system second order intermodulation intercept Variation in system third order intermodulation intercept Input compression LO second harmonic interference level LNA second harmonic interference level Quadrature gain match Quadrature phase match I & Q ...
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Characteristic LO SSB phase noise LO integrated phase jitter LOTEST output amplitude (specifications apply with both single-ended and differential load unless otherwise stated) Bandwidth Bandwidth absolute tolerance Channel bandwidth match Characteristic response Channel gain match Channel phase match Output total ...
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IM2’. AGC set to deliver an output of 0.5 Vp-p with an input CW @ frequency fc of -25 dBm. Two undesired tones at fc+146 and fc+155 MHz @ -11 dBm generating output intermodulation spur at 9 ...
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Zarlink Semiconductor 2004 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...