CH7303 ETC [List of Unclassifed Manufacturers], CH7303 Datasheet

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... The DVI processor includes a low jitter PLL for generation of the high frequency serialized clock, and all circuitry required to encode, serialize and transmit data. The CH7303 is able to drive a DFP display at a pixel rate 165MHz, supporting UXGA resolution displays. No scaling of input data is performed on the data output to the DVI device ...

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... DE 3 VREF DGND 7 GPIO[1] / HPINT 8 GPIO[0] 9 HPDET DGND 12 DVDD 13 RESET* 14 SPD 15 SPC 16 AGND 2 Chrontel CH7303 Figure 2: 64-Pin LQFP Package 209-0000-031 CH7303 48 H SYNC 47 V SYNC 46 D[12] 45 VDDV 44 AVDD 43 D[13] 42 D[14] 41 AGND 40 GND 39 B/Pb 38 R/Pr 37 G/Y 36 N/C 35 ISET 34 GND 33 VDD Rev. 0.4, 8/26/2002 ...

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... TGND using short and wide traces. DVI Data Channel 0 Outputs These pins provide the DVI differential outputs for data channel 0 (blue). DVI Data Channel 1 Outputs These pins provide the DVI differential outputs for data channel 1 (green). CH7303 Description 3 ...

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... The levels are 0 to VDDV, and the VREF signal is used as the threshold level. External Clock Inputs These inputs form a differential clock signal input to the CH7303 for use with the and D[14:0] data. If differential clocks are not available, the XCLK* input should be connected to VREF. ...

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... HDTV / EDTV Bypass In HDTV / EDTV Bypass mode, data, sync and clock signals are input to the CH7303 from a graphics device in the scanning method that matches the display device (interlaced data is sent to the CH7303 to drive an interlaced display, non-interlaced data is sent to the CH7303 to drive a non-interlaced display). The input data format can be YCrCb or RGB ...

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... DDR). For the multiplexed data, clock at 2X pixel rate the data applied to the CH7303 is latched with one edge of the clock (also known as single edge transfer mode or SDR). The polarity of the pixel clock can be reversed under serial port control. In single edge transfer modes, the clock edge used to latch data is programmable ...

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... Input Data Formats The CH7303 supports 9 different multiplexed data formats, each of which can be used with a 1X clock latching data on both clock edges clock latching data with a single edge (rising or falling depending on the value of the MCP bit – rising refers to a rising edge on the XCLK signal, a falling edge on the XCLK* signal). The input data formats are ...

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... Table 6: Multiplexed Input Data Formats (IDF = 2, 3) IDF = Format = Pixel # P0a P0b Bus Data D[11] G0[4] R0[7] D[10] G0[3] R0[6] D[9] G0[2] R0[5] D[8] B0[7] R0[4] D[7] B0[6] R0[3] D[6] B0[5] G0[7] D[5] B0[4] G0[6] D[4] B0[3] G0[5] 8 SAV P0a P0b 0 12-bit RGB P0b P1a P1b P0a G1[3] R1[7] G0[4] R0[6] G1[2] R1[6] G0[3] R0[5] G1[1] R1[5] G0[2] R0[4] G1[0] R1[4] B0[7] R0[3] B1[7] R1[3] B0[6] R0[2] B1[6] R1[2] B0[5] R0[1] B1[5] R1[1] B0[4] R0[0] B1[4] R1[0] B0[3] G0[7] B1[3] G1[7] G0[0] G0[6] B1[2] G1[6] B0[2] G0[5] B1[1] G1[5] B0[1] G0[4] B1[0] G1[4] B0[0] 2 RGB 5-6-5 P1a P1b P0a G1[4] R1[7] G0[5] G1[3] R1[6] G0[4] G1[2] R1[5] G0[3] B1[7] R1[4] B0[7] B1[6] R1[3] B0[6] B1[5] G1[7] B0[5] B1[4] G1[6] B0[4] B1[3] G1[5] B0[3] CH7303 P1a P1b P2a P2b 1 12-bit RGB P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[5] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 3 RGB 5-5-5 P0b P1a P1b X G1[5] X R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] B1[7] R1[5] R0[4] B1[6] R1[4] R0[3] B1[5] R1[3] G0[7] B1[4] G1[7] G0[6] B1[3] G1[6] 209-0000-031 Rev. 0.4, 8/26/2002 ...

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... Cb2[7] 0 S[6] Cb2[6] 0 S[5] Cb2[5] 0 S[4] Cb2[4] 0 S[3] Cb2[3] 0 S[2] Cb2[2] 0 S[1] Cb2[1] 0 S[0] Cb2[ 15-bit RGB P0b P0a P0b R0[9] R0[4] R0[9] R0[8] R0[3] R0[8] R0[7] R0[2] R0[7] R0[6] R0[1] R0[6] R0[5] R0[0] R0[5] R0[4] G0[4] G0[9] R0[3] G0[3] G0[8] R0[2] G0[2] G0[7] R0[1] G0[1] G0[6] R0[0] G0[0] G0[5] G0[9] B0[4] B0[9] G0[8] B0[3] B0[8] G0[7] B0[2] B0[7] G0[6] B0[1] B0[6] G0[5] B0[0] B0[5] CH7303 P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] Y3[2] Y2[1] Cr2[1] Y3[1] Y2[0] Cr2[0] Y3[0] P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] Y3[2] Y2[1] Cr2[1] Y3[1] Y2[0] Cr2[0] Y3[0] 8 15-bit RGB P0a P0b R0[8] R0[9] R0[6] R0[7] R0[4] R0[5] R0[2] R0[3] R0[0] R0[1] G0[8] G0[9] G0[6] G0[7] ...

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... Recommended Operating Conditions Symbol Description AVDD PLL Power Supply Voltage VDD DAC Power Supply Voltage DVDD Digital Power Supply Voltage VDDV I/O Power Supply Voltage R Output load to DAC Outputs L 10 CH7303 Min Typ Max -0.5 5.0 GND – 0.5 VDD + 0.5 Indefinite 0 85 -65 150 150 220 ...

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... 3.3V 0 -0.4mA DVDD-0 3.2mA OL TVDD = 3.3V ± 5% TVDD – = 50Ω ± 0.01 TERM = 2400Ω ± TVDD – SWING 0.6 400 TVDD – 0.01 CH7303 Typ Max Units 10 10 bits 33 TBD 0.06 mA Typ Max Unit 0.4 V VDD + 0 DVDD+0.5 V Vref-0 ...

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... XCLK f = 165MHz 75 XCLK f = 165MHz XCLK f = 165MHz XCLK f = 165MHz XCLK XCLK = XCLK* to TBD D[11:0 Vref D[11:0 TBD Vref to XCLK = XCLK* 50 209-0000-031 CH7303 - refers to GPIOx, RESET*, AS and Typ Max Unit 165 MHz 242 ps 242 1.2 ns 150 Rev. 0.4, ...

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... Table 10: Timing for Clock - Slave, Sync - Slave Mode Symbol Parameter t2 XCLK & XCLK* rise/fall time w/15pF load t3 D[11:0 & DE rise/fall time w/ 15pF load 209-0000-031 Rev. 0.4, 8/26/2002 PIXELS 1 VGA Line t3 CH7303 P0a P0b P1a P1b P2a P2b Min Typ Max 3 3 ...

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... CHRONTEL 4.0 Package Dimensions Table of Dimensions No. of Leads Milli- MIN 12 10 meters MAX SYMBOL 0.17 1.35 0.05 0.50 0.27 1.45 0.15 Figure 6: 64 Pin LQFP Package CH7303 LEAD CO-PLANARITY E .004 “ 0.45 0.09 0° 1.00 0.75 0.20 7° 209-0000-031 Rev. 0.4, 8/26/2002 ...

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... Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. 2002 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A. 209-0000-031 Rev. 0.4, 8/26/2002 Disclaimer Chrontel 2210 O’Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com CH7303 15 ...