GAL22V10B-25QP Lattice Semiconductor, GAL22V10B-25QP Datasheet

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GAL22V10B-25QP

Manufacturer Part Number
GAL22V10B-25QP
Description
Generic Logic Array
Manufacturer
Lattice Semiconductor
Datasheet

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• HIGH PERFORMANCE E
• ACTIVE PULL-UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
• E
• TEN OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
ESCRIPTION
The GAL22V10, at 4ns maximum propagation delay time, combines
a high performance CMOS process with Electrically Erasable (E
floating gate technology to provide the highest performance avail-
able of any 22V10 device on the market. CMOS circuitry allows
the GAL22V10 to consume much less power when compared to
bipolar 22V10 devices. E
erase times, providing the ability to reprogram or reconfigure the
device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
22v10_09
Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Features
Description
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS
— Fully Function/Fuse-Map/Parametric Compatible
— 90mA Typical Icc on Low Power Device
— 45mA Typical Icc on Quarter Power Device
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
with Bipolar and UVCMOS 22V10 Devices
®
Advanced CMOS Technology
2
technology offers high speed (<100ms)
2
CMOS
®
TECHNOLOGY
2
)
1
Functional Block Diagram
Pin Configuration
NC
I
I
I
I
I
I
I/CLK
11
5
7
9
12
4
I
I
I
I
I
I
I
I
I
I
I
GAL22V10
GAL22V10
Specifications GAL22V10
Top View
Top View
SOIC
14
PLCC
2
High Performance E
28
16
26
18
25
23
21
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
Generic Array Logic™
GAL22V10
PRESET
RESET
10
12
14
16
16
12
10
14
I/CLK
8
GND
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
I
I
I
I
I
I
I
I
I
I
1
6
12
22V10
DIP
GAL
2
CMOS PLD
August 2004
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
24
18
13
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/O/Q

Related parts for GAL22V10B-25QP

GAL22V10B-25QP Summary of contents

Page 1

... GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

Page 2

GAL22V10 Ordering Information Conventional Packaging Commercial Grade Specifications ...

Page 3

Lead-Free Packaging Commercial Grade Specifications ...

Page 4

Output Logic Macrocell (OLMC) The GAL22V10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 14 and 23, DIP pinout), two have ten product terms (pins ...

Page 5

Registered Mode ACTIVE LOW Combinatorial Mode ACTIVE LOW Specifications GAL22V10 ...

Page 6

GAL22V10 Logic Diagram / JEDEC Fuse Map 1 ( 0000 0044 . . . 0396 0440 . . . . 0880 2 (3) 0924 . . . . . 1452 3 (4) 1496 . . . . ...

Page 7

Absolute Maximum Ratings Supply voltage V ....................................... CC Input voltage applied ........................... -2 Off-state output voltage applied ........... -2 Storage Temperature .................................. -65 to 150°C Ambient Temperature with Power Applied ......................................... -55 to 125°C 1. Stresses ...

Page 8

AC Switching Characteristics TEST PARAM 1 COND Input or I/O to Combinatorial Output Clock to Output Delay — Clock to Feedback Delay t su — Setup Time, Input or Fdbk before ...

Page 9

AC Switching Characteristics TEST DESCRIPTION PARAM. COND Input or I/O to Comb. Output Clock to Output Delay — Clock to Feedback Delay t su — Setup Time, Input or Fdbk ...

Page 10

Switching Waveforms INPUT or I/O FEEDBACK COMBINATORIAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis OUTPUT Input or I/O to Output Enable/Disable CLK (w/o fdbk) Clock Width INPUT or I/O ...

Page 11

Descriptions max with External Feedback 1/( Note: fmax with external feedback is cal- culated from ...

Page 12

Switching Test Conditions Input Pulse Levels Input Rise and D-4/-5/-7 Fall Times D-10/-15/-20/-25 Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (except D-4) (see figure below) ...

Page 13

... The electronic signature is an additional feature not present in other manufacturers' 22V10 devices. To use the extra feature of the user-programmable electronic signature it is necessary to choose a Lattice Semiconductor 22V10 device type when com- piling a set of logic equations. In addition, many device program- mers have two separate selections for the device, typically a GAL22V10 and a GAL22V10-UES (UES = User Electronic Sig- nature) or GAL22V10-ES ...

Page 14

Power-Up Reset INTERNAL REGISTER Q - OUTPUT ACTIVE LOW OUTPUT REGISTER ACTIVE HIGH OUTPUT REGISTER Circuitry within the GAL22V10 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q out- puts set low ...

Page 15

GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.1 1.05 RISE FALL 1 0.95 0.9 4.5 4.75 5 5.25 Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 RISE FALL 1.1 1 0.9 0.8 -55 -25 ...

Page 16

GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams Vol vs Iol 0.6 0.4 0 Iol (mA) Normalized Icc vs Vcc 1.2 1.1 1 0.9 0.8 4.5 4.75 5 5.25 Supply Voltage ...

Page 17

GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.1 RISE 1.05 FALL 1 0.95 0.9 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tpd vs Temp 1.3 RISE 1.2 FALL 1.1 1 0.9 0.8 -55 ...

Page 18

GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams Vol vs Iol 0.5 0.4 0.3 0.2 0 Iol (mA) Normalized Icc vs Vcc 1.15 1.1 1.05 1 0.95 0.9 0.85 4.5 4.75 5 5.25 ...

Page 19

GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.1 RISE 1.05 FALL 1 0.95 0.9 4.5 4.75 5 5.25 5.5 Supply Voltage (V) Normalized Tpd vs Temp 1.3 RISE 1.2 FALL 1.1 ...

Page 20

GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams Vol vs Iol 0.6 0.4 0 Iol (mA) Normalized Icc vs Vcc 1.2 1.1 1 0.9 0.8 4.5 4.75 ...

Page 21

Specifications GAL22V10 21 Notes ...

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