8521BYLFT IDT, 8521BYLFT Datasheet

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8521BYLFT

Manufacturer Part Number
8521BYLFT
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 8521BYLFT

Rohs
yes
Part # Aliases
ICS8521BYLFT
G
The ICS8521 is a low skew, 1-to-9 Differential-to-HSTL
Fanout Buffer. The ICS8521 has two selectable clock
inputs. The CLK, nCLK pair can accept most standard
differential input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels. The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8521 ideal for today’s
most advanced applications, such as IA64 and static RAMs.
B
8521BY
CLK_SEL
CLK_EN
LOCK
ENERAL
nPCLK
PCLK
nCLK
CLK
D
IAGRAM
D
0
1
ESCRIPTION
D
LE
Q
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
www.idt.com
1
F
• 9 HSTL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input
• PCLK, nPCLK supports the following input types:
• Maximum output frequency: 500MHz
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.8ns (maximum)
• V
• 3.3V core, 1.8V output operating supply voltages
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
P
levels: LVPECL, LVDS, HSTL, SSTL, HCSL
LVPECL, CML, SSTL
EATURES
IN
OH
D
CLK_SEL
= 1.4V (maximum)
A
CLK_EN
IFFERENTIAL
nPCLK
PCLK
SSIGNMENT
nCLK
GND
CLK
V
DD
7mm x 7mm x 1.4mm Package Body
1
2
3
4
5
6
7
8
3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5
9 1 0 1 1 1 2 1 3 1 4 1 5 16
-
32-Lead LQFP
TO
ICS8521
Y Package
-HSTL F
Top View
L
OW
ANOUT
S
ICS8521
KEW
24
23
22
21
20
19
18
17
REV. E JULY 25, 2010
V
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
, 1-
B
DDO
DDO
UFFER
TO
-9

Related parts for 8521BYLFT

8521BYLFT Summary of contents

Page 1

... PCLK Q2 nQ2 6 nPCLK 7 GND Q3 nQ3 8 CLK_EN nQ4 Q5 nQ5 32-Lead LQFP Q6 nQ6 7mm x 7mm x 1.4mm Package Body Q7 nQ7 Q8 nQ8 www.idt.com 1 ICS8521 KEW TO -HSTL F B ANOUT UFFER 24 V DDO nQ3 21 Q4 ICS8521 20 nQ4 ...

Page 2

... www.idt.com 2 ICS8521 KEW - -HSTL F TO ANOUT ...

Page 3

... " www.idt.com 3 ICS8521 KEW - -HSTL ANOUT ...

Page 4

... www.idt.com 4 ICS8521 KEW - -HSTL F TO ANOUT = 0°C 70° ...

Page 5

... www.idt.com 5 ICS8521 KEW - -HSTL ANOUT = 0°C 70° ...

Page 6

... AC T ORE UTPUT OAD nQx Qx nQy Qy t sk( UTPUT KEW nCLK, nPCLK CLK, PCLK nQ0:nQ8 Q0: ROPAGATION ELAY nQ0:nQ8 Q0:Q8 Pulse Width t PERIOD t PW odc = t PERIOD odc & ERIOD 8521BY D IFFERENTIAL M I EASUREMENT NFORMATION V DD SCOPE Qx nCLK, nPCLK V PP CLK, ...

Page 7

... For example, if the input DD clock swing is only 2.5V and V and R2/R1 = 0.609 CLK_IN + V_REF - C1 R2 0.1uF INGLE NDED IGNAL RIVING IFFERENTIAL www.idt.com 7 ICS8521 KEW - -HSTL ANOUT EVELS = 3.3V, V_REF should be 1.25V DD I NPUT REV. E JULY 25, 2010 -9 TO UFFER ...

Page 8

... HiPerClockS Input F 3B. IGURE 3.3V 3.3V LVDS_Driv er CLK nCLK HiPerClockS Input 3D. IGURE 3.3V R4 125 CLK nCLK HiPerClockS Input OUPLE www.idt.com 8 ICS8521 KEW - -HSTL ANOUT 3. Ohm CLK Ohm nCLK HiPerClockS Input CLK/ CLK I ...

Page 9

... CML D RIVER 3.3V 3.3V R4 125 3.3V LVPECL PCLK nPCLK HiPerClockS Input R5 R2 100 - 200 84 F 4D. IGURE 3.3V 3.3V LVDS PCLK nPCLK HiPerClockS PCLK/nPCLK F 4F. IGURE www.idt.com 9 ICS8521 KEW - -HSTL ANOUT 3. Ohm PCLK R1 100 nPCLK Ohm HiPerClockS PCLK/nPCLK PCLK/nPCLK I D NPUT RIVEN B -I ...

Page 10

... IFFERENTIAL P C OWER ONSIDERATIONS = 3. 3.465V, which gives worst case results 3.465V * 80mA = 277.2mW * Pd_total + for 32-pin LQFP, Forced Convection by Velocity (Linear Feet per Minute 67.8°C/W 47.9°C/W www.idt.com 10 ICS8521 KEW TO - -HSTL ANOUT UFFER must be used. Assuming a JA ...

Page 11

... DDO_MAX OL_MAX Pd_H = (1.0V/50Ω) * (2V - 1.0V) = 20mW Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW 8521BY D IFFERENTIAL V DDO Q1 5. HSTL RIVER IRCUIT AND ) ) www.idt.com 11 ICS8521 KEW - -HSTL F TO ANOUT V OUT RL 50Ω ERMINATION REV. E JULY 25, 2010 ...

Page 12

... OUNT The transistor count for ICS8521 is: 944 8521BY D IFFERENTIAL R I ELIABILITY NFORMATION 32 L LQFP EAD θ θ θ θ θ by Velocity (Linear Feet per Minute 67.8°C/W 47.9°C/W www.idt.com 12 ICS8521 KEW TO - -HSTL ANOUT UFFER 200 500 55.9°C/W 50.1°C/W 42.1° ...

Page 13

... ° www.idt.com 13 ICS8521 KEW - -HSTL ANOUT ° ...

Page 14

... Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ...

Page 15

... www.idt.com 15 ICS8521 KEW - -HSTL ANOUT ...

Page 16

... San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners ...

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