DSPIC33EP128MC506-I/MR Microchip Technology, DSPIC33EP128MC506-I/MR Datasheet - Page 152
DSPIC33EP128MC506-I/MR
Manufacturer Part Number
DSPIC33EP128MC506-I/MR
Description
Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 64P OpAmps
Manufacturer
Microchip Technology
Type
dsPIC33E/PIC24Er
Datasheet
1.DSPIC33EP128MC506-IMR.pdf
(510 pages)
Specifications of DSPIC33EP128MC506-I/MR
Rohs
yes
Core
dsPIC33E
Data Bus Width
16 bit
Program Memory Size
128 KB
Data Ram Size
16 KB
Maximum Clock Frequency
7.37 MHz, 32 kHz
Number Of Programmable I/os
53
Number Of Timers
5 x 16-bit, 2 x 32-bit
Device Million Instructions Per Second
70 MIPs
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-64
Mounting Style
SMD/SMT
Family / Core
dsPIC33E/PIC24E
Interface Type
CAN, I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
Yes
Product
DSPs
Program Memory Type
Flash
Supply Current
10 mA
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
9.1
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X family of devices
provide seven system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with Phase-Locked Loop (PLL)
• FRC Oscillator with postscaler
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Low-Power RC (LPRC) Oscillator
FIGURE 9-2:
EQUATION 9-2:
EQUATION 9-3:
DS70657F-page 152
Where,
N1 = PLLPRE + 2
N2 = 2 x (PLLPOST + 1)
M = PLLDIV + 2
Note 1:
F
F
IN
SYS
PLLPRE<4:0>
CPU Clocking System
0.8 MHz < F
=
F
÷ N1
IN
This frequency range must be met at all times.
------ -
N1
M
PLLI
PLL BLOCK DIAGRAM
F
F
OSC
VCO
F
=
F
(1)
OSC
PLLI
F
< 8.0 MHz
IN
CALCULATION
CALCULATION
=
F
------------------------------------ -
IN
PLLPRE
PFD
PLLDIV
-------------------- -
N1 N2
M
+
+
2
2
PLLDIV<8:0>
=
VCO
÷ M
F
120 MH
IN
--------------------------------------------------------------------------------------- -
Z
PLLPRE
F
< F
SYS
Instruction execution speed or device operating
frequency, F
EQUATION 9-1:
Figure 9-2
Equation 9-2
frequency (F
Equation 9-3
frequency (F
SYS
(1)
+
PLLDIV
PLLPOST<1:0>
< 340 MH
2
is a block diagram of the PLL module.
CY
÷ N2
IN
IN
2 PLLPOST
) and output frequency (F
) and VCO frequency (F
provides the relation between input
provides the relation between input
, is given by
+
Z
2
2011-2012 Microchip Technology Inc.
F
CY
F
DEVICE OPERATING
FREQUENCY
F
F
OSC
OSC
= Fosc/2
OSC
+
Equation
1
120 MHz @ +125ºC
140 MHz @ +85ºC
9-1.
SYS
OSC
).
).
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