DSPIC33EP128MC506-I/PT Microchip Technology, DSPIC33EP128MC506-I/PT Datasheet - Page 277
DSPIC33EP128MC506-I/PT
Manufacturer Part Number
DSPIC33EP128MC506-I/PT
Description
Digital Signal Processors & Controllers - DSP, DSC 16B 128KB FL 16KBR 60MHz 64P OpAmps
Manufacturer
Microchip Technology
Type
dsPIC33E/PIC24Er
Datasheet
1.DSPIC33EP128MC506-IMR.pdf
(510 pages)
Specifications of DSPIC33EP128MC506-I/PT
Rohs
yes
Core
dsPIC33E
Data Bus Width
16 bit
Program Memory Size
128 KB
Data Ram Size
16 KB
Maximum Clock Frequency
7.37 MHz, 32 kHz
Number Of Programmable I/os
53
Number Of Timers
5 x 16-bit, 2 x 32-bit
Device Million Instructions Per Second
70 MIPs
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-64
Mounting Style
SMD/SMT
Family / Core
dsPIC33E/PIC24E
Interface Type
CAN, I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
Yes
Product
DSPs
Program Memory Type
Flash
Supply Current
10 mA
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33EP128MC506-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 277 of 510
- Download datasheet (9Mb)
REGISTER 19-1:
2011-2012 Microchip Technology Inc.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
When performing Master operations, ensure that the IPMIEN bit is ‘0’.
STREN: SCLx Clock Stretch Enable bit (when operating as I
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
ACKDT: Acknowledge Data bit (when operating as I
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(when operating as I
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
0 = Acknowledge sequence not in progress
RCEN: Receive Enable bit (when operating as I
1 = Enables Receive mode for I
0 = Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0 = Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
0 = Repeated Start condition not in progress
SEN: Start Condition Enable bit (when operating as I
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0 = Start condition not in progress
Hardware clear at end of master Acknowledge sequence.
master Repeated Start sequence.
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
2
C master, applicable during master receive)
2
C. Hardware clear at end of eighth bit of master receive data byte.
2
C master)
2
2
2
C master, applicable during master receive)
C master)
C master)
2
C slave)
2
C master)
DS70657F-page 277
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