IS49NLC36160-25EBL ISSI, IS49NLC36160-25EBL Datasheet

Page 1

... IS49NLC96400,IS49NLC18320,IS49NLC36160 576Mb (x9, x18, x36) Common I/O RLDRAM FEATURES • 400MHz DDR operation (800Mb/s/pin data rate) • 28.8Gb/s peak bandwidth (x36 at 400 MHz clock frequency) • Reduced cycle time (15ns at 400MHz) • 32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms) • ...

Page 2

... IS49NLC96400,IS49NLC18320,IS49NLC36160 1 Package Ball out and Description 1.1 576Mb (64Mx9) Common I/O BGA Ball-out (Top View VREF VSS VEXT 3 B VDD DNU DNU 3 C VTT DNU DNU A22 DNU DNU 3 E A21 DNU DNU DNU DNU BA2 ...

Page 3

... IS49NLC96400,IS49NLC18320,IS49NLC36160 1.2 576Mb (32Mx18) Common I/O BGA Ball-out (Top View VREF VSS A 4 VDD DNU B 4 VTT DNU A22 DNU A21 DNU DNU BA2 DK# L REF# CS# M WE# A16 4 N A18 DNU DQ14 ...

Page 4

... IS49NLC96400,IS49NLC18320,IS49NLC36160 1.3 576Mb (16Mx36) Common I/O BGA Ball-out (Top View VREF VSS B VDD DQ8 C VTT DQ10 1 D A22 DQ12 2 E A21 DQ14 A5 DQ16 BA2 A9 J DK0 DK0# K DK1 DK1# L REF# CS# M WE# A16 N A18 DQ24 P A15 DQ22 R VSS QK1 T VTT DQ20 ...

Page 5

... IS49NLC96400,IS49NLC18320,IS49NLC36160 1.4 Ball Descriptions Symbol Type Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE A* Input REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. BA* Input Bank address inputs: Selects to which internal bank a command is being applied to. ...

Page 6

... IS49NLC96400,IS49NLC18320,IS49NLC36160 2 Electrical Specifications 2.1 Absolute Maximum Ratings Item I/O Voltage Voltage on V supply relative to V EXT Voltage on V supply relative Voltage on V supply relative to V DDQ Note: Stress greater than those listed in this table may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

Page 7

... IS49NLC96400,IS49NLC18320,IS49NLC36160 2.4 Operating Conditions and Maximum Limits Description Condition Standby t = idle; All banks idle; No inputs toggling CK current Active CS# =1; No commands; Bank address incremented and standby half address/data change once every 4 clock cycles current BL=2; Sequential bank access; Bank transitions once every t ; Half address transitions once every t RC followed by write sequence ...

Page 8

... IS49NLC96400,IS49NLC18320,IS49NLC36160 Notes: 1) IDD specifications are tested after the device is properly initialized. +0°C ≤ /2. DDQ MIN MIN Definitions for IDD conditions: a. LOW is defined as V ≤ V (AC) MAX HIGH is defined as V ≥ V (AC) MIN Stable is defined as inputs remaining at a HIGH or LOW level. ...

Page 9

... IS49NLC96400,IS49NLC18320,IS49NLC36160 ( 2.7 AC Electrical Characteristics Description Symbol Input clock cycle time t CK Input data clock cycle time t DK (5, 6) Clock jitter: period t JITPER Clock jitter: t JITCC cycle-to-cycle Clock HIGH time t /t CKH DKH Clock LOW time t /t CKL DKL Clock to input data ...

Page 10

... IS49NLC96400,IS49NLC18320,IS49NLC36160 Notes: 1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with V signals. 2. Outputs measured with equivalent load: 3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operations are tested for the full voltage range specified. ...

Page 11

... IS49NLC96400,IS49NLC18320,IS49NLC36160 Clock Input Example CK# V /2+0.15V, V (AC) MAX DDQ DDQ V /2-0.15V, V (AC) MIN DDQ IX CK Notes: 1. DKx and DKx# have the same requirements as CK and CK#. 2. All voltages referenced Tests for AC timing, IDD and electrical AC and DC characteristics may be conducted at normal reference/supply voltage levels; but the related specifications and device operations are tested for the full voltage range specified ...

Page 12

... IS49NLC96400,IS49NLC18320,IS49NLC36160 3 Functional Descriptions (1) 3.1 Power-up and Initialization ® The RLDRAM 2 Memory must be powered-up and initialized using the specific steps listed below: 1. Apply power by ramping up supply voltages V Power-up sequence begins when both V time as V and V . Once the supply voltages are stable, clock inputs CK/CK# and DK/DK# can be applied. Register NOP ...

Page 13

... IS49NLC96400,IS49NLC18320,IS49NLC36160 3.3 Power-up and Initialization Timing Diagram Non-multiplexed Address Mode EXT DDQ REF CK# NOP Command Notes recommended that the address input signals be driven LOW during the dummy MRS commands. 2. A10–A17 must be LOW. 3. DLL must be reset are changed ...

Page 14

... IS49NLC96400,IS49NLC18320,IS49NLC36160 5. CK and CK# must be separated at all times to prevent invalid commands from being issued. 6. The Auto Refresh commands can be issued in any order with respect to the 1,024 NOP commands. However, timing parameter t any valid command (Any bank after an AREF command to the same bank has been issued. ...

Page 15

... IS49NLC96400,IS49NLC18320,IS49NLC36160 The Mode Register Set command stores the data for controlling the various operating modes of the memory using address inputs A0-A17 as mode registers. During the MRS command, the cycle time and the read/write latency of the memory can be selected from different configurations. The MRS command also programs the memory to operate in either Multiplexed Address Mode or Non- multiplexed Address Mode ...

Page 16

... IS49NLC96400,IS49NLC18320,IS49NLC36160 Mode Register Diagram (Multiplexed Address Mode Mode Register 1 A10-18 A10-18 M10- ODT DLL Config A0 M0 Ay4 Ay3 Ax0 ...

Page 17

... IS49NLC96400,IS49NLC18320,IS49NLC36160 3.5 Mode Register Bit Description Configuration The cycle time and read/write latency can be configured from the different options shown in the Mode Register Diagram. In order to maximize data bus utilization, the WRITE latency is equal to READ latency plus one. The read and write latencies are increased by one clock cycle during multiplexed address mode compared to non-multiplexed mode ...

Page 18

... IS49NLC96400,IS49NLC18320,IS49NLC36160 Address Mapping in Multiplexed Address Mode Data Width Burst Length 2 x36 X18 Note Don’t Care. On-Die Termination (ODT) If the ODT is enabled, the DQs and DM are terminated to V are not terminated. Figure 3.1 shows the equivalent circuit receiver with ODT. The ODT function is dynamically switched off when a DQ begins to drive after a READ command is issued ...

Page 19

... IS49NLC96400,IS49NLC18320,IS49NLC36160 3.6 Deselect/No Operation (DESL/NOP) The Deselect command is used to prevent unwanted operations from being performed in the memory device during wait or idle states. Operations already registered to the memory prior to the assertion of the Deselect command will not be cancelled. 3.7 Read Operation (READ) The Read command performs burst-oriented data read accesses in a bank of the memory device. The Read command is initiated by registering the WE# and REF# signals logic HIGH while the CS logic LOW state ...

Page 20

... IS49NLC96400,IS49NLC18320,IS49NLC36160 CKH CKL CK# CK Command RD Address BA2, A2 QVLD DQ t CKQK QKx# QKx Notes: 1. Minimum READ data valid window can be expressed as MIN and t are recommended to have 50% / 50% duty. CKH CKL referenced to DQ0–DQ17 in x36 and DQ0–DQ8 in x18. t QKQ0 4 ...

Page 21

... IS49NLC96400,IS49NLC18320,IS49NLC36160 ADDRESS ADDRESS CKDK DKx# DKx Command WR NOP Address BA1 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00F, 12/4/2012 Non-Multiplexed Mode CK# CK CS# WE# REF# ADDRESS A BANK BANK BA* ADDRESS Write Command 2 3 NOP NOP NOP Write Latency = 5 Basic WRITE Burst with DM Timing: BL=4 & WL=5 ...

Page 22

... IS49NLC96400,IS49NLC18320,IS49NLC36160 0 1 CK# CK Command WR NOP Address BA1,A1 DKx DKx# DQ QVLD QKx QKx# 3.9 Auto Refresh Command (AREF) The Auto Refresh command performs a refresh cycle on one row of a specific bank of the memory. Only bank addresses are required together with the control the pins. Therefore, Auto Refresh commands can be issued on subsequent CK clock cycles on both multiplexed and non-multiplexed address mode ...

Page 23

... IS49NLC96400,IS49NLC18320,IS49NLC36160 3.10 Command Truth Table Operation Device DESELECT/No Operation Mode Register Set Read Write Auto Refresh Notes "Don't Care;" logic HIGH logic LOW Valid Address Valid Bank Address. 2. During MRS, only address inputs A0-A17 are used. 3. Address width changes with burst length. ...

Page 24

... IS49NLC96400,IS49NLC18320,IS49NLC36160 3.11 On-Die Termination (ODT) Timing Examples. 0 CK# CK Command RD Address BA2, A2 QVLD DQ ODT DQ QKx# QKx 0 CK# CK Command RD Address BA2, A2 DKx# DKx QVLD DQ ODT DQ QKx# QKx Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00F, 12/4/2012 NOP NOP NOP Read Latency = 4 t QKVLD DQ ODT on Read Operation with ODT: RL=4 & ...

Page 25

... IS49NLC96400,IS49NLC18320,IS49NLC36160 4 IEEE 1149.1 TAP and Boundary Scan ® RLDRAM 2 Memory devices have a serial boundary-scan test access port (TAP) that allow the use of a limited set of JTAG instructions to test the interconnection between the memory I/Os and printed circuit board traces or other components. In conformance with IEEE Standard 1149.1, the memory contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register ...

Page 26

... IS49NLC96400,IS49NLC18320,IS49NLC36160 4.3 TAP Controller State and Block Diagram Test Logic Reset Run Test Idle 0 TDI TMS TCK Note: 113 boundary scan registers in RLDRAM Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00F, 12/4/2012 Select Capture DR 0 Shift Exit1 DR ...

Page 27

... IS49NLC96400,IS49NLC18320,IS49NLC36160 4.4 Performing a TAP Reset A Reset is performed by forcing TMS HIGH (V and does not affect its operation. At 4.5 TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK ...

Page 28

... IS49NLC96400,IS49NLC18320,IS49NLC36160 4.7 TAP Instruction Set Many instructions are possible with an eight-bit instruction register and all valid combinations are listed in the TAP Instruction Code Table. All other instruction codes that are not listed on this table are reserved and should not be used. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO ...

Page 29

... IS49NLC96400,IS49NLC18320,IS49NLC36160 4.8 TAP DC Electrical Characteristics and Operating Conditions (+0°C ≤ T ≤ +95°C; +1.7V ≤ V ≤ +1.9V, unless otherwise noted Description Input high (logic 1) voltage Input low (logic 0) voltage Input leakage current Output leakage current Output Disabled, 0V ≤ V Output low voltage Output low voltage ...

Page 30

... IS49NLC96400,IS49NLC18320,IS49NLC36160 4.10 TAP Timing THTL TLTH Test Mode Clock (CK) t MVTH Test Mode Select (TMS) Test Data-In (TDI) Test Data-Out (TDO) 4.11 TAP Instruction Codes Instruction Code EXTEST 0000 0000 IDCODE 0010 0001 SAMPLE/PRELOAD 0000 0101 CLAMP 0000 0111 High-Z 0000 0011 ...

Page 31

... IS49NLC96400,IS49NLC18320,IS49NLC36160 4.14 Boundary Scan Order Signal name Bump Bit# x9 x18 x36 DK1 2 DK# DK# DK1# 3 CS# CS# CS# 4 REF# REF# REF# 5 WE# WE# WE# 6 A17 A17 A17 7 A16 A16 A16 8 A18 A18 A18 9 A15 A15 A15 10 DNU DQ14 DQ25 11 DNU DQ14 DQ25 12 DNU DNU ...

Page 32

... Rev. 00F, 12/4/2012 Order Part No. Organization IS49NLC96400-25EB 64M x 9 IS49NLC96400-25EBL 64M x 9 IS49NLC18320-25EB 32M x 18 IS49NLC18320-25EBL 32M x 18 IS49NLC36160-25EB 16M x 36 IS49NLC36160-25EBL 16M x 36 IS49NLC96400-25B 64M x 9 IS49NLC96400-25BL 64M x 9 IS49NLC18320-25B 32M x 18 IS49NLC18320-25BL 32M x 18 IS49NLC36160-25B 16M x 36 IS49NLC36160-25BL 16M x 36 ...

Page 33

... Rev. 00F, 12/4/2012 Order Part No. Organization IS49NLC96400-25EBI 64M x 9 IS49NLC96400-25EBLI 64M x 9 IS49NLC18320-25EBI 32M x 18 IS49NLC18320-25EBLI 32M x 18 IS49NLC36160-25EBI 16M x 36 IS49NLC36160-25EBLI 16M x 36 IS49NLC96400-25BI 64M x 9 IS49NLC96400-25BLI 64M x 9 IS49NLC18320-25BI 32M x 18 IS49NLC18320-25BLI 32M x 18 IS49NLC36160-25BI 16M x 36 IS49NLC36160-25BLI 16M x 36 ...

Page 34

... IS49NLC96400,IS49NLC18320,IS49NLC36160 Ball Grid Array Package Code: B (144-ball) Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00F, 12/4/2012 34 ...