IS49NLC36160-25EBL ISSI, IS49NLC36160-25EBL Datasheet - Page 28

• Manufacturer Part Number: IS49NLC36160-25EBL
• Description: DRAM 576M, x36, 400Mhz RLDRAM2
• Manufacturer: ISSI

Specifications of IS49NLC36160-25EBL

• Rohs: yes
• Organization: 16 M x 36
• Package / Case: FBGA-144
• Memory Size: 576 Mbit
• Maximum Clock Frequency: 400 MHz
• Access Time: 2.5 ns
• Supply Voltage - Max: 2.63 V
• Supply Voltage - Min: 2.38 V
• Maximum Operating Current: 380 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT

IS49NLC96400,IS49NLC18320,IS49NLC36160
4.7 TAP Instruction Set
Many instructions are possible with an eight-bit instruction register and all valid combinations are listed in the TAP Instruction Code
Table. All other instruction codes that are not listed on this table are reserved and should not be used. Instructions are loaded into
the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state,
instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the
TAP controller must be moved into the Update-IR state.
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register cells at output balls
are used to apply a test vector, while those at input balls capture test results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of
EXTEST, the output driver is turned on, and the PRELOAD data is driven onto the output balls.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the identification register. It also places the
identification register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller
enters the shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP
controller is given a test logic reset state.
High-Z
®
The High-Z instruction causes the bypass register to be connected between the TDI and TDO. This places all RLDRAM
2 Memory
outputs into a High-Z state.
CLAMP
When the CLAMP instruction is loaded into the instruction register, the data driven by the output balls are determined from the
values held in the boundary scan register.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the capture-DR state, a
snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP
controller clock can only operate at a frequency up to 50 MHz, while the memory clock operates significantly faster. Because there is
a large difference between the clock frequencies, it is possible that during the capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is
no guarantee as to the value that will be captured. Repeatable results may not be possible. To ensure that the boundary scan
register will capture the correct value of a signal, the memory signal must be stabilized long enough to meet the TAP controller’s
capture setup plus hold time (t
plus t
). The memory clock input might not be captured correctly if there is no way in a design to
CS
CH
stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out
the data by putting the TAP into the shift-DR state. This places the boundary scan register between the TDI and TDO balls.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the bypass register is
placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple
devices are connected together on a board.
Integrated Silicon Solution, Inc. – www.issi.com –
28
Rev. 00F, 12/4/2012