IDT74SSTV16859PAG IDT, Integrated Device Technology Inc, IDT74SSTV16859PAG Datasheet

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IDT74SSTV16859PAG

Manufacturer Part Number
IDT74SSTV16859PAG
Description
IC BUFFER 13-26BIT SSTL 64-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
74SSTVr
Datasheet

Specifications of IDT74SSTV16859PAG

Logic Type
13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs
Supply Voltage
2.3 V ~ 2.7 V
Number Of Bits
13, 26
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74SSTV16859PAG
FEATURES:
• 2.3V to 2.7V Operation
• SSTL_2 Class II style data inputs/outputs
• Differential CLK input
• RESET control compatible with LVCMOS levels
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using
• Available in 56 pin VFQFPN and 64 pin TSSOP packages
INDUSTRIAL TEMPERATURE RANGE
APPLICATIONS:
• Ideally suited for DIMM DDR registered applications
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDT74SSTV16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
c
machine model (C = 200pF, R = 0)
2008 Integrated Device Technology, Inc.
RESET
V
CLK
CLK
REF
D
1
51
48
49
45
35
13-BIT TO 26-BIT REGISTERED
BUFFER WITH SSTL I/O
TO 12 OTHER CHANNELS
1
DESCRIPTION:
2.7V V
are SSTL_2 level compatible with JEDEC standard for SSTL_2.
power-up phase. RESET, which can be operated independent of CLK and
CLK, must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
registers, and force all outputs to a low state, before a stable clock has been
applied. With inputs held low and a stable clock applied, outputs will remain
low during the Low-to-High transition of RESET.
The SSTV16859 is a 13-bit to 26-bit registered buffer designed for 2.3V-
RESET is an LVCMOS input since it must operate predictably during the
RESET, when in the low state, will disable all input receivers, reset all
DD
and supports low standby operation. All data inputs and outputs
1D
R
C1
INDUSTRIAL TEMPERATURE RANGE
IDT74SSTV16859
16
32
NOVEMBER 2008
Q
Q
1A
1B
DSC-5947/9

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IDT74SSTV16859PAG Summary of contents

Page 1

IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: • 2.3V to 2.7V Operation • SSTL_2 Class II style data inputs/outputs • Differential CLK input • RESET control compatible with LVCMOS levels • Latch-up performance exceeds 100mA • ESD ...

Page 2

IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O PIN CONFIGURATIONS GND Q 13B V DDQ Q 12B Q 11B Q 10B ...

Page 3

IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O PIN DESCRIPTION Pin Names Description Data Output 1 13 GND Ground V Output-stage drain power voltage DDQ V Logic power voltage DD RESET Asynchronous reset input - resets ...

Page 4

IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O OPERATING CHARACTERISTICS, T Symbol Parameter V Supply Voltage DD V Output Supply Voltage DDQ V Reference Voltage ( REF REF DDQ V Termination Voltage TT V Input Voltage I ...

Page 5

IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O TEST CIRCUITS AND WAVEFORMS (V LVCMOS RESET Input t INACT I 10% DD (see note 2) Voltage and Current Waveforms Inputs Active and Inactive Times t W Input ...

Page 6

IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O ORDERING INFORMATION XX XX SSTV Temp. Range Family Device Type Package PA NL 859 16 74 CORPORATE HEADQUARTERS San Jose, CA 95138 6 INDUSTRIAL TEMPERATURE RANGE Thin Shrink ...

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