SSTUF32864EHLF IDT, Integrated Device Technology Inc, SSTUF32864EHLF Datasheet

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SSTUF32864EHLF

Manufacturer Part Number
SSTUF32864EHLF
Description
IC REGIST BUFF 25BIT DDR2 96-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of SSTUF32864EHLF

Logic Type
Configurable Registered Buffer for DDR2
Supply Voltage
1.7 V ~ 1.9 V
Number Of Bits
25, 14
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
96-BGA
Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Inputs
25
Number Of Outputs
25
High Level Output Current
-8mA
Low Level Output Current
8mA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Mounting
Surface Mount
Pin Count
96
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SSTUF32864EHLF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
SSTUF32864EHLFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
25-Bit Configurable Registered Buffer for DDR2
Recommended Application:
Product Features:
Truth Table
0987B—09/28/04
RST#
H
H
H
H
H
H
H
H
H
H
H
H
L
DDR2 Memory Modules
Provides complete DDR DIMM solution with
ICS97U877
Ideal for DDR2 400, 533 and 667
25-bit 1:1 or 14-bit 1:2 configurable registered buffer
Supports SSTL_18 JEDEC specification on data
inputs and outputs
Supports LVCMOS switching levels on C0, C1 and
RESET# inputs
Low voltage operation
V
Available in 96 BGA package
Drop-in replacement for ICSSSTUF32866
Green packages available
DD
Floating
DCS#
X or
= 1.7V to 1.9V
L
L
L
L
L
L
H
H
H
H
H
H
Integrated
Circuit
Systems, Inc.
Floating
CSR#
X or
L
L
H
H
H
H
H
H
L
L
L
L
I nputs
Floating
L or H
L or H
L or H
L or H
X or
CK
Floating
L or H
L or H
L or H
L or H
X or
CK#
Floating
DODT,
DCK E
X or
Dn,
L
H
X
L
H
X
L
H
X
L
H
X
Qn
Q
Q
Q
Q
Q
Q
L
H
L
H
L
H
L
0
0
0
0
0
0
Outputs
QCS#
Q
Q
Q
Q
H
H
H
H
L
L
L
L
L
0
0
0
0
QODT,
QCKE
Q
Q
Q
Q
L
L
H
L
H
L
H
L
H
0
0
0
0
M
A
D
G
H
K
N
B
C
E
F
L
P
R
T
J
DCKE
D2
D3
DODT
D5
D6
NC
CK
CK#
D8
D9
D10
D11
D12
D13
D14
1:1 Register (C0 = 0, C1 = 0)
1
M
A
B
C
D
E
F
G
H
J
K
L
N
P
R
T
NC
D15
D16
NC
D17
D18
RST#
DCS#
CSR#
D19
D20
D21
D22
D23
D24
D25
ICSSSTUF32864A
Pin Configuration
Ball Assignments
2
1
96 Ball BGA
(Top View)
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
V
2
REF
DD
DD
DD
DD
DD
DD
DD
REF
3
3
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
GND
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
4
4
5
QCKE
Q2
Q3
QODT
Q5
Q6
C1
QCS#
ZOH
Q8
Q9
Q10
Q11
Q12
Q13
Q14
6
5
NC
Q15
Q16
NC
Q17
Q18
C0
NC
ZOL
Q19
Q20
Q21
Q22
Q23
Q24
Q25
6

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SSTUF32864EHLF Summary of contents

Page 1

Integrated Circuit Systems, Inc. 25-Bit Configurable Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97U877 • Ideal for DDR2 400, 533 and 667 Product Features: • 25-bit 1:1 or 14-bit 1:2 ...

Page 2

Ball Assignments DCKE REF GND GND DODT NC GND GND GND GND ...

Page 3

Ball Assignment ...

Page 4

Block Diagram for 1:1 mode (positive logic) RST# CK CK# V REF DCKE DODT DCS# CSR Other Channels *Note: Disabled in 1:1 configuration 0987B—09/28/04 ICSSSTUF32864A ...

Page 5

Block Diagram for 1:2 mode (positive logic) RST# CK CK# V REF DCKE DODT DCS# CSR Other Channels *Note: Disabled in 1:1 configuration 0987B—09/28/04 ICSSSTUF32864A ...

Page 6

Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Supply Voltage . . . . . . . . . . ...

Page 7

Electrical Characteristics - 70° 2.5 +/-0.2V (unless otherwise stated SYMBOL PARAMETERS All Inputs V I Standby (Static) RESET# ...

Page 8

Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL PARAMETERS f Clock frequency clock Pulse duration, CK, CK High or Low t W Differential inputs active time (See notes 1 and 2) t ACT Differential inputs inactive ...

Page 9

CK Inputs Test Point R = 100 L Test Point VCMOS RST Inp act I DD (see 10% Note 2) VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES t w Inpu t V ...

Page 10

LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT Output VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT Output VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT Figure 7 — Output Slew-Rate M easurement I nfor mation (V Notes ...

Page 11

A1 D TOP VIEW E ALL DIMENSIONS IN MILLIMETERS Min/Max 16.00 Bsc 5.50 Bsc 1.30/1.50 13.50 Bsc 5.50 Bsc 1.30/1.50 7.00 Bsc 4.50 Bsc 0.86/1.00 Note: Ball grid total indicates maximum ball count for package. Lesser quantity ...

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