LCMXO2280E-3TN100C Lattice, LCMXO2280E-3TN100C Datasheet - Page 16

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LCMXO2280E-3TN100C

Manufacturer Part Number
LCMXO2280E-3TN100C
Description
CPLD - Complex Programmable Logic Devices 2280 LUTs 73 IO 1.2V -3 Spd
Manufacturer
Lattice
Datasheet

Specifications of LCMXO2280E-3TN100C

Rohs
yes
Memory Type
SRAM
Number Of Macrocells
1140
Maximum Operating Frequency
500 MHz
Delay Time
5.1 ns
Number Of Programmable I/os
73
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Factory Pack Quantity
450
Supply Current
20 mA
Supply Voltage - Max
1.26 V
Supply Voltage - Min
1.14 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LCMXO2280E-3TN100C
Manufacturer:
LATTICE
Quantity:
25
Part Number:
LCMXO2280E-3TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 2-13. Memory Core Reset
For further information on the sysMEM EBR block, see the details of additional technical documentation at the end
of this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-14. The GSR input to the
EBR is always asynchronous.
Figure 2-14. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR sig-
nal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-14. The reset timing
rules apply to the RPReset input vs the RE input and the RST input vs. the WE and RE inputs. Both RST and
RPReset are always asynchronous EBR inputs.
These instructions apply to all EBR RAM, ROM and FIFO implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled
GSRN
RSTA
RSTB
Programmable Disable
Reset
Clock
Clock
Enable
Memory Core
2-13
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
MachXO Family Data Sheet
Port A[17:0]
Port B[17:0]
MAX
(EBR clock). The reset
Architecture

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